Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))

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概要

• 論文の詳細を見る

• Efforts have been devoted to maximizing memory array densities. However, as the devices are scaled down in dimension and getting closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are proposed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as the representative, and investigate the paired cell interference (PCI) which inevitably occurs in the read operation for 3-D memory devices in this feature. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.

• 社団法人電子情報通信学会の論文
• 2007-06-18

著者

• Park Byung-gook

  School Of Electrical Engineering Seoul National University

• Park Il

  Inter-university Semiconductor Research Center Seoul National University:school Of Electrical Engine

• Lee J

  School Of Electrical Engineering Seoul National University

• Cho Seongjae

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu

• LEE Jong

  School of Electrical Engineering, Seoul National University

• SHIN Hyungcheol

  School of Electrical Engineering, Seoul National University

• Lee J

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Yun Jang‐gn

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Lee Jong

  School Of Adv. Mat. Sci. & Eng. Sungkyunkwan Univ.

• Kim Doo‐hyun

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Lee Joung-eob

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• PARK Il

  School of Electrical Engineering, Seoul National University

• CHO Seongjae

  School of Electrical Engineering and Computer Science, Seoul National University

• LEE Jung

  School of Electrical Engineering and Computer Science, Seoul National University

• YUN Jang-Gn

  School of Electrical Engineering and Computer Science, Seoul National University

• KIM Doo-Hyun

  School of Electrical Engineering and Computer Science, Seoul National University

• Shin Hyungcheol

  School Of Electrical Engineering And Computer Science Seoul National University

• Yun Jang

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu

• Lee Jong

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat

• Lee Jong

  Inter-university Semiconductor Research Center School Of Electrical Engineering Seoul Nat'l Uni

• Yur Jang-gn

  School Of Electrical Engineering Seoul National University

• Park Byung-gook

  School Of Electrical Engineering And Computer Sciences And The Inter-university Semiconductor Resear

• Park Byung-Gook

  School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Shinlim-Dong, Kwanak-Gu, Seoul 151-742, Korea

• Park Byung-Gook

  School of Electrical Engineering & Inter-University Semiconductor Research Center (ISRC), Seoul National University, Shilim-Dong, Kwanak-Gu, Seoul 151-742, Republic of Korea

• Lee Jung

  School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu 702-701, Korea

• Shin Hyungcheol

  School of Electrical Eng.

• Park Byung-Gook

  School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea

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