Park Byung-gook | School Of Electrical Engineering Seoul National University

スポンサーリンク

概要

関連著者

もっと見る

著作論文

A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs)
An Analytic Current-Voltage Equation for Top-contact OTFTs Including the Effects of Variable Series Resistance
Spatial Distribution of Channel Thermal Noise in Short-Channel MOSFETs
Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
Improving the Cell Characteristics Using SiN Liner at Active Edge in 4G NAND Flash
Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
Accurate Extraction of Mobility, Effective Channel Length, and Source/Drain Resistance in 60nm MOSFETs
Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
Monte Carlo Simulation of Single-Electron Nanocrystal Memories
4-bit FinFET SONOS flash memory: Optimization of structure and 3D numerical simulation (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
4-bit FinFET SONOS flash memory: Optimization of structure and 3D numerical simulation (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
A New 1T DRAM Cell : Cone Type 1T DRAM Cell
Effects of Conductive Defects on Unipolar RRAM for the Improvement of Resistive Switching Characteristics
Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)
Comparative Study on Top- and Bottom-Source Vertical-Channel Tunnel Field-Effect Transistors
Study on Threshold Voltage Control of Tunnel Field-Effect Transistors Using V_T-Control Doping Region

もっと見る

スポンサーリンク