Shin Hyungcheol | Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu

スポンサーリンク

概要

関連著者

もっと見る

著作論文

A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
An Analytic Current-Voltage Equation for Top-contact OTFTs Including the Effects of Variable Series Resistance
Spatial Distribution of Channel Thermal Noise in Short-Channel MOSFETs
Low Hysteresis Organic Thin-Film Transistors and Inverters with Hybrid Gate Dielectric
Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
16GHz CMOS LNA design without Source degeneration inductor (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
FN Stress Induced Degradation on Random Telegraph Signal Noise in Deep Submicron NMOSFETs
Investigating programming motivation sources from student behavior (教育工学)
Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs(Ultra-Thin Gate Insulators,Fundamentals and Applications of Advanced Semiconductor Devices)
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
Accurate Extraction of Mobility, Effective Channel Length, and Source/Drain Resistance in 60nm MOSFETs
RF Linearity Analysis of FinFETs using 3-D Device Simulation (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
RF Linearity Analysis of FinFETs using 3-D Device Simulation (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)
Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)

もっと見る

スポンサーリンク