Choi Woo | Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University, ENG 420-016, Sillim-dong, Gwank-gu, Seoul 151-722, Korea
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概要
- Choi Woo Youngの詳細を見る
- 同名の論文著者
- Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University, ENG 420-016, Sillim-dong, Gwank-gu, Seoul 151-722, Koreaの論文著者
関連著者
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Choi Woo
Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University, ENG 420-016, Sillim-dong, Gwank-gu, Seoul 151-722, Korea
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Choi Woo
Inter-university Semiconductor Research Center Seoul National University
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Lee Jong
Inter-univ. Semicon. Res. Center Seoul Nat. Univ.
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Park Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea
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Park Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea
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PARK Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu
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CHOI Woo
Inter-University Semiconductor Research Center, Seoul National University
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Choi W
Inter-university Semiconductor Research Center Seoul National University
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LEE Jong
Inter-University Semiconductor Research Center, Seoul National University
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Lee J
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
著作論文
- Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
- Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
- Nanoscale Multi-Line Patterning Using Sidewall Structure
- Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure
- Nanoscale Poly-Si Line Formation and Its Uniformity
- Nanoscale Poly-Si Line Formation and Its Uniformity
- Design and Simulation of Asymmetric MOSFETs(Junction Formation and TFT Reliability,Fundamentals and Applications of Advanced Semiconductor Devices)
- Novel Gate-All-Around MOSFETs with Self-Aligned Structure
- Multi-Functionality of Novel Structured Tunneling Devices
- Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)