Choi B | Seoul National Univ. Seoul Kor
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概要
関連著者
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CHOI Byung
Inter-University Semiconductor Research Center, Seoul National University
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Choi B
Seoul National Univ. Seoul Kor
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PARK Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu
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LEE Jong
Inter-University Semiconductor Research Center, Seoul National University
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Choi Byung
Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U
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Lee Jong
Inter-univ. Semicon. Res. Center Seoul Nat. Univ.
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Park Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea
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CHOI Woo
Inter-University Semiconductor Research Center, Seoul National University
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Choi W
Inter-university Semiconductor Research Center Seoul National University
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Park Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea
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Choi Woo
Inter-university Semiconductor Research Center Seoul National University
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Choi Woo
Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University, ENG 420-016, Sillim-dong, Gwank-gu, Seoul 151-722, Korea
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Lee J
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
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Woo Dong-soo
Inter-university Semiconductor Research Center Seoul National University
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Woo Dong-soo
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat
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Choi Young
Inter-university Semiconductor Research Center Seoul National University:school Of Electrical Engine
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Sim Jae
Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U
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SUNG Suk
Inter-University Semiconductor Research Center, School of Electrical Engineering, Seoul Nat'l Univ.
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Kang Sangwoo
Seoul National Univ. Seoul Kor
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Lee Myeong
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat
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Sung Suk
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
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Kang In
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat
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Kang Sangwoo
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
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WOO Dong
Inter-University Semiconductor Research Center, Seoul National University
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PARK Byung
Inter-University Semiconductor Research Center, School of Electrical Engineering, Seoul Nat'l Univ.
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Lee Y
Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U
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Sim Jae
School Of Electrical Engineering & Inter-university Semiconductor Research Center (isrc) Seoul N
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Song Ki-whan
Inter-university Semiconductor Research Center School Of Electrical Engineering Seoul National Unive
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LEE Yong
Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National
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SONG Ki
Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National
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PARK Donggun
Device Research Team, R&D Center, Samsung Electronics Co.
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CHUNG Chilhee
C&M, System LSI, Samsung Electronics Co.
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Chung Chilhee
C&m System Lsi Samsung Electronics Co.
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Lee long
Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul Na
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Park Byung
Inter-univ. Semicon. Res. Center Seoul Nat. Univ.
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Lee Long
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat
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Sim J‐s
Seoul National Univ. Seoul Kor
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Park Donggun
Device Research Team
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Park Donggun
Device Research Team R&d Center Samsung Electronics Co.
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Kang Sangwoo
Inter-university Semiconductor Research Center Seoul National University:school Of Electrical Engine
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Song Ki
Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U
著作論文
- Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
- Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
- A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology
- Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
- Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
- Stable Extraction of Threshold Voltage Using Transconductance Change Method for CMOS Modeling, Simulation and Characterization
- Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-5Onm Low-Power and High-Speed MOSFET Design(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
- Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
- Side-Gate Design for 50nm Electrically Induced Source/Drain MOSFETs
- Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
- 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As^+_2 Low Energy Implantations
- 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As_2^+ Å Low Energy Ion Implantations