Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain

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概要

• 論文の詳細を見る
• 社団法人応用物理学会の論文
• 2002-04-30

著者

• PARK Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• Choi Young

  Inter-university Semiconductor Research Center Seoul National University:school Of Electrical Engine

• CHOI Woo

  Inter-University Semiconductor Research Center, Seoul National University

• CHOI Byung

  Inter-University Semiconductor Research Center, Seoul National University

• WOO Dong

  Inter-University Semiconductor Research Center, Seoul National University

• LEE Jong

  Inter-University Semiconductor Research Center, Seoul National University

• Choi B

  Seoul National Univ. Seoul Kor

• Choi W

  Inter-university Semiconductor Research Center Seoul National University

• Choi Woo

  Inter-university Semiconductor Research Center Seoul National University

• Lee J

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Woo Dong-soo

  Inter-university Semiconductor Research Center Seoul National University

• Lee Jong

  Inter-univ. Semicon. Res. Center Seoul Nat. Univ.

• Choi Byung

  Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Choi Woo

  Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University, ENG 420-016, Sillim-dong, Gwank-gu, Seoul 151-722, Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

関連論文

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• Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
• Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
• Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
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• Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
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