Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)

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概要

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• For reproducible and controllable characteristics of the device, Si-based single electron transistors with electrically formed tunneling barriers and a quantum dot are fabricated on the basis of the sidewall process technique. The fabricated devices are based on silicon on insulator (SOI) with the poly-Si sidewall gates. A dual-gate single electron transistor (DG-SET) that is compatible to the complementary metal-oxide-semiconductor (CMOS) process and self-aligned is presented. The performance of previous versions of the DG-SET was limited by the innate parasitic MOSFET current. Through modified structure and simulations, these elements are confirmed. To solve such issues, a new type of DG-SET having the extended channel is introduced using the process of shallow doping and the TEOS sidewall patterning technique. Characteristics of the device are compared with those of previous DG-SETs through device simulation. Simulation results clearly obtained electrically formed tunneling barriers and quantum dot. Moreover, the MOSFET current in the newly proposed structure is significantly lower than that in the previous structure, when the control gate bias is increased. This property of proposed device is expected to contribute for room temperature operation.

• 2010-06-23

著者

• KANG Kwon-Chil

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• LEE Joung-Eob

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• LEE Jung

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• PARK Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• Park Byung‐gook

  School Of Electrical Engineering Seoul National University

• Lee J

  School Of Electrical Engineering Seoul National University

• Lee Jong-eob

  Inter-University Semiconductor Research Center (ISRC)

• Wan Kim

  Inter-University Semiconductor Research Center (ISRC)

• Lee J

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Kang Kwon-chil

  Inter-university Semiconductor Research Center (isrc):school Of Electrical Engineering And Computer

• Wan Kim

  Inter-university Semiconductor Research Center (isrc):school Of Electrical Engineering And Computer

• Lee Jung

  Inter-University Semiconductor Research Center (ISRC):School of Electrical Engineering and Computer Science, Seoul National University

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC):School of Electrical Engineering and Computer Science, Seoul National University

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Lee Jung

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

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