Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
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概要
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In this paper, characteristics of the 2-bit recessed channel memory with lifted-charge trapping nodes are investigated. The length between the charge trapping nodes through channel, which is defined as the effective memory node length (Meff), is extended by lifting up them. The dependence of VTH window and short channel effect (SCE) on the recessed depth is analyzed. Improvement of short channel effect is achieved because the recessed channel structure increases the effective channel length (Leff). Moreover, this device shows highly scalable memory characteristics without suffering from the bottom-side effect (BSE).
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著者
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LEE Jung
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu
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CHO Seongjae
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu
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PARK Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu
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Lee Gil
Inter-university Semiconductor Research Center Seoul National University:school Of Electrical Engine
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LEE Jong
Inter-University Semiconductor Research Center, Seoul National University
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Park Il
Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National
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Lee J
School Of Electrical Engineering Seoul National University
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Kim Doo-Hyun
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
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Kim Yoon
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
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YUN Jang
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
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Kim Yoon
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
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