Dual Gate Single-Electron Transistors with a Recessed Channel and Underlapped Source/Drain Structure

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概要

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• In this work, we have fabricated and characterized the dual gate single-electron transistors (DG-SETs). This device has recessed channel and underlapped source/drain structure. Fabrication flow and device structure are described as well as operation schemes. Clear Coulomb oscillation peaks and negative differential trans-conductance curve are observed at room temperature (300 K). Measurement results obtained at period of Coulomb oscillation is 0.9 V due to an ultra-small control gate capacitance, and oscillation peaks are shifted through the sidewall gate bias. Also, in order to confirm that single electron tunneling is caused by the electrically induced tunneling barriers, and not by random fluctuations along the silicon-on-insulator (SOI) active, room temperature measurement results for device with different parameters is compared.

• 2010-11-25

著者

• KANG Kwon-Chil

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• LEE Joung-Eob

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• PARK Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• Yun Jang-gn

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu

• Kim Dae-hwan

  School Of Electrical Engineering Kookmin University

• Shin Hyungcheol

  Inter-university Semiconductor Research Center (isrc)

• Kim Garam

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Computer Science Seoul National University

• Lee Jong-Ho

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

• Lee Jung-Han

  Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Korea

• Lee Joung-Eob

  Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Kang Kwon-Chil

  Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Korea

• Kim Garam

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

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