Dynamic driving current using side gate bias of single-electron transistors

スポンサーリンク

概要

• 論文の詳細を見る

著者

• KANG Kwon-Chil

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• LEE Joung-Eob

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• Shin Hyungcheol

  Inter-university Semiconductor Research Center (isrc)

• Lee Jong-Ho

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

• Lee Jung-Han

  Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Korea

• Kim Garam

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

• Kim Kyung-Wan

  Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea

関連論文

• Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
• Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
• Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
• Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
• Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
• Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
• Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
• Nanoscale Multi-Line Patterning Using Sidewall Structure
• Single-Electron MOS Memory with a Defined Quantum Dot Based on Conventional VLSI Technology
• Single-Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
• Single Electron Memory with a Defined Poly-Si Dot Based on Conventional VLSI Technology
• Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and Its Modeling
• Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
• Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
• Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
• Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
• Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
• Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
• 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
• Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
• Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
• 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
• Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs)
• An Analytic Current-Voltage Equation for Top-contact OTFTs Including the Effects of Variable Series Resistance
• Low Hysteresis Organic Thin-Film Transistors and Inverters with Hybrid Gate Dielectric
• Pentacene TFTs Fabricated by High-aspect Ratio Metal Shadow Mask
• Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
• Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
• Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
• Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
• Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
• Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
• Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
• Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
• Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
• 16GHz CMOS LNA design without Source degeneration inductor (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
• Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
• Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
• 3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
• Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
• Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
• FN Stress Induced Degradation on Random Telegraph Signal Noise in Deep Submicron NMOSFETs
• Full-swing pentacene organic inverter with long-channel driver and short-channel load
• A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology
• Silicon Quantum Tunneling Devices - FIBTET and MOSET
• Indium Doped nMOSFETs and Buried Channel pMOSFETs with n^+ Polysilicon Gate
• Channel Doping Engineering with Indium as an Alternative p-Type Dopant
• Investigating programming motivation sources from student behavior (教育工学)
• Nanoscale Poly-Si Line Formation and Its Uniformity
• Nanoscale Poly-Si Line Formation and Its Uniformity
• Design and Simulation of Asymmetric MOSFETs(Junction Formation and TFT Reliability,Fundamentals and Applications of Advanced Semiconductor Devices)
• Novel Gate-All-Around MOSFETs with Self-Aligned Structure
• Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs(Ultra-Thin Gate Insulators,Fundamentals and Applications of Advanced Semiconductor Devices)
• Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
• Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• RF Linearity Analysis of FinFETs using 3-D Device Simulation (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
• RF Linearity Analysis of FinFETs using 3-D Device Simulation (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
• Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption
• Investigation of Threshold Voltage Disturbance Caused by Programmed Adjacent Cell in Virtual Source/Drain NAND Flash Memory
• Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)
• Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)
• Fin and Recess-Channel Metal Oxide Semiconductor Field Effect Transistor for Sub-50 nm Dynamic Random Access Memory Cell
• Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories
• Room-Temperature Operation of a Single-Electron Transistor Made by Oxidation Process Using the Recessed Channel Structure
• Dual Gate Single-Electron Transistors with a Recessed Channel and Underlapped Source/Drain Structure
• Silicon-Based Dual-Gate Single-Electron Transistors for Logic Applications
• Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor
• Extraction of Interface-States Energy Distribution in Nitrided and Pure Gate Dielectrics for Metal Oxide Semiconductor Field Effect Transistor Applications
• Accurate Extraction of Excess Channel Thermal Noise Coefficient in Berkeley Short-Channel Insulated Gate Field-Effect Transistor Model 4
• Dynamic driving current using side gate bias of single-electron transistors
• Self-Aligned Dual-Gate Single-Electron Transistors
• Study on Threshold Voltage Control of Tunnel Field-Effect Transistors Using VT-Control Doping Region
• Extraction of Electron Band Mobility in Amorphous Silicon Thin-Film Transistors
• Comparative Study on Top- and Bottom-Source Vertical-Channel Tunnel Field-Effect Transistors
• Study on Threshold Voltage Control of Tunnel Field-Effect Transistors Using V_T-Control Doping Region
• Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultralow-Power Logic Circuits
• Dual-Gate Single-Electron Transistor with Silicon Nano Wire Channel and Surrounding Side Gates
• A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device
• Electrically Stable Organic Thin-Film Transistors and Circuits Using Organic/Inorganic Double-Layer Insulator
• Self-Aligned Asymmetric Metal–Oxide–Semiconductor Field Effect Transistors Fabricated on Silicon-on-Insulator
• Capacitorless Dynamic Random Access Memory Cell with Highly Scalable Surrounding Gate Structure
• On the Characteristics and Spatial Dependence of Channel Thermal Noise in Nanoscale Metal–Oixde–Semiconductor Field Effect Transistors
• Enhancement of Radiative Recombination by Different Indium Composition of Multiple Quantum Barriers in GaN-Based Light-Emitting Diodes
• An Analytic Current–Voltage Equation for Top-Contact Organic Thin Film Transistors Including the Effects of Variable Series Resistance
• L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications
• Enhancement of Radiative Recombination by Different Indium Composition of Multiple Quantum Barriers in GaN-Based Light-Emitting Diodes (Special Issue : Microprocesses and Nanotechnology)
• 16GHz CMOS LNA design without Source degeneration inductor (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))

もっと見る 閉じる

スポンサーリンク