Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs

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概要

• 論文の詳細を見る

• 50nm-long MOSFETs with two poly-Si side-gate spacers were designed. The optimization of side-gate length was investigated in the viewpoint of short channel effect, current drivability, and hot carrier effect that is dependent on the variation of the side-gate length. Two-dimensional and two-carrier device simulations of the biased side-gate MOSFET were carried out to optimize the side-gate length. The results of device simulation, such as threshold voltage roll-off, I_<ON>-I_<OFF> and substrate current characteristics, suggest that the condition of the same side-gate length as that of the main-gate promises the optimal transistor operation in terms of the immunity to short channel effect and hot carrier effect, and the improvement of current drivability in the 50nm biased side-gate MOSFET.

• 社団法人電子情報通信学会の論文
• 2001-06-28

著者

• PARK Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• Choi Young

  Inter-university Semiconductor Research Center Seoul National University:school Of Electrical Engine

• CHOI Woo

  Inter-University Semiconductor Research Center, Seoul National University

• CHOI Byung

  Inter-University Semiconductor Research Center, Seoul National University

• LEE Jong

  Inter-University Semiconductor Research Center, Seoul National University

• Choi B

  Seoul National Univ. Seoul Kor

• Choi W

  Inter-university Semiconductor Research Center Seoul National University

• Choi Woo

  Inter-university Semiconductor Research Center Seoul National University

• Lee Jong

  Inter-univ. Semicon. Res. Center Seoul Nat. Univ.

• Choi Byung

  Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Choi Woo

  Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University, ENG 420-016, Sillim-dong, Gwank-gu, Seoul 151-722, Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

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