Silicon-Based Dual-Gate Single-Electron Transistors for Logic Applications

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概要

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• We have fabricated silicon-based dual-gate single-electron transistors (DG-SETs) with electrically induced tunneling barriers. By utilizing e-beam lithography patterning and additional oxidation process, the device is scaled down beyond the previously demonstrated dual-gate structures. As a result, Coulomb oscillation is maintained in the large control gate bias region and its oscillation period is increased to 2.3 V. Based on the measurement, SET SPICE model is optimized and useful complementary metal–oxide–semiconductor (CMOS)/SET circuits which reduce the current oscillation period or improve peak-to-valley current ratio (PVCR) are investigated by using the model.

• 2009-07-25

著者

• LEE Dong

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• YANG Hong-Seon

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• KANG Kwon-Chil

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• LEE Joung-Eob

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• LEE Jung

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• PARK Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• PARK Sang

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci

• Park Byung-Gook

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Sillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Lee Dong

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Sillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea

• Lee Jung

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Kang Kwon-Chil

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Sillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea

• Park Sang

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Sillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea

• Yang Hong-Seon

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Sillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

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