Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs)
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概要
- 論文の詳細を見る
- 2007-09-19
著者
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LEE Joung-Eob
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu
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PARK Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu
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Park Byung‐gook
School Of Electrical Engineering Seoul National University
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Park Byung-gook
School Of Electrical Engineering Seoul National University
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Lee J
School Of Electrical Engineering Seoul National University
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Kang Sangwoo
Seoul National Univ. Seoul Kor
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KANG Sangwoo
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
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KIM Dae-Hwan
School of Electrical Engineering, Kookmin University
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PARK Il-Han
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
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KIM Jin-Ho
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
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LEE Jong-Duk
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
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Lee J
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
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Lee Joung-eob
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
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Sim Jae
Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U
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Lee Jong
Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U
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Kang Sangwoo
Inter-university Semiconductor Research Center Seoul National University:school Of Electrical Engine
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Park Il-han
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
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Kim Dae-hwan
School Of Electrical Engineering Kookmin University
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Kim Jin-ho
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
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Lee Jong
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat
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Lee Jong
Inter-university Semiconductor Research Center School Of Electrical Engineering Seoul Nat'l Uni
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Kang Sangwoo
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu
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Kang Sangwoo
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
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Park Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea
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Lee Jong-Duk
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, #059, 599 Gwanangno, Gwanak-gu, Seoul 151-744, Korea
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Park Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea
関連論文
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- Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
- Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
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- Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
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- Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
- Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
- Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
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- Design and Simulation of Asymmetric MOSFETs
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- Stable Extraction of Threshold Voltage Using Transconductance Change Method for CMOS Modeling, Simulation and Characterization
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- Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
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- 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As^+_2 Low Energy Implantations
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