A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology

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概要

• 論文の詳細を見る
• 2004-09-15

著者

• PARK Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• CHOI Byung

  Inter-University Semiconductor Research Center, Seoul National University

• LEE Jong

  Inter-University Semiconductor Research Center, Seoul National University

• Choi B

  Seoul National Univ. Seoul Kor

• Lee J

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Lee Y

  Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

• Sim Jae

  School Of Electrical Engineering & Inter-university Semiconductor Research Center (isrc) Seoul N

• Sim Jae

  Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

• Song Ki-whan

  Inter-university Semiconductor Research Center School Of Electrical Engineering Seoul National Unive

• LEE Yong

  Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National

• SONG Ki

  Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National

• PARK Donggun

  Device Research Team, R&D Center, Samsung Electronics Co.

• CHUNG Chilhee

  C&M, System LSI, Samsung Electronics Co.

• Chung Chilhee

  C&m System Lsi Samsung Electronics Co.

• Sim J‐s

  Seoul National Univ. Seoul Kor

• Park Donggun

  Device Research Team

• Park Donggun

  Device Research Team R&d Center Samsung Electronics Co.

• Lee Jong

  Inter-univ. Semicon. Res. Center Seoul Nat. Univ.

• Choi Byung

  Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

• Song Ki

  Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

関連論文

• Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
• A new cone-type 1T DRAM cell (Electron devices)
• Independent Gate Twin-bit SONOS flash memory with split-gate effect (Silicon devices and materials)
• Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
• Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
• Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
• Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
• Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
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• Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and Its Modeling
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• Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
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