Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
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概要
- 論文の詳細を見る
Efforts have been devoted to maximizing memory array densities. However, as the devices are scaled down in dimension and getting closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are proposed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as the representative, and investigate the paired cell interference (PCI) which inevitably occurs in the read operation for 3-D memory devices in this feature. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.
- （社）電子情報通信学会の論文
著者
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LEE Jung
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu
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CHO Seongjae
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu
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PARK Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu
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LEE Jong
Inter-University Semiconductor Research Center, Seoul National University
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Lee J
School Of Electrical Engineering Seoul National University
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Kim Doo-Hyun
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
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Yun Jang-Gn
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
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Shin Hyungcheol
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
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PARK Han
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
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