Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))

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概要

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• Recently, demands for the high-density non-volatile memory products are exploding. ln this paper, we have fabricated and characterized nanoscale SONOS flash memories, which are expected to replace the currently-dominant poly-silicon floating gate structures. We have fabricated 30-nm x 30-nm channel Single Bit Cell (SBC) and 90-nm x 100-nm channel Double Bit Cell (DBC) which has 2 bits per a cell. Since NAND type SBCs are fabricated by using the sidewall patterning technique, they show uniform memory performances in spite of fine channel length of 30-nm. NOR type DBCs are fabricated with the merged-triple gate structure by using inverted sidewall patterning technique, which separates the charge storage nodes physically. This scheme completely solves the problems of the charge redistribution and diffusion in the nitride layer, which are expected to be the major drawbacks of conventional 2-bit SONOS devices (i.e. NROMs) in the nanoscale regime. The new cell structures have shown excellent performance and reliability characteristics in the 90-nm channel length.

• 社団法人電子情報通信学会の論文
• 2004-06-24

著者

• PARK Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• Park Byung-gook

  Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

• Lee Young

  Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National

• Park Il

  Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National

• Kim Chung

  MD Lab., Samsung Advanced Institute of Technology

• Park Dong

  Device Research Team, R&D Center, Samsung Electronics Co. Ltd.

• Kim Chung

  Md Lab. Samsung Advanced Institute Of Technology

• Park B‐g

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Lee Y

  Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

• Park Dong

  Device Research Team R&d Center Samsung Electronics Co. Ltd.

• Park Il

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Park Il

  Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

• Lee Young

  Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Park Il

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

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