Self-Aligned Dual-Gate Single-Electron Transistors

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概要

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• A novel complementary metal–oxide–semiconductor (CMOS) process compatible and self-aligned fabrication method for the dual-gate single-electron transistor (DG-SET) is presented. The performance of previous versions of the DG-SET was limited by inherent parasitic elements and its fabrication process was divergent from conventional CMOS, limiting the possibility of co-integration. Through simulation, the parasitic elements are confirmed to be caused by the non-self-alignment of the control gate, side gates, and source/drain. To resolve such issues, a new type of DG-SET was fabricated using a self-aligned process. Measurement results obtained at room temperature revealed clear Coulomb oscillation peaks in the trans-conductance curve. Through parameter extraction and its comparison with previous results, this is confirmed to be the consequence of single-electron tunneling. Also, in order to confirm that the single-electron tunneling is caused by the electrically induced tunneling barriers, and not by random fluctuations along the SOI active, low temperature measurement results for devices with different parameters is compared.

• 2008-04-25

著者

• LEE Joung-Eob

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• PARK Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• PARK Il-Han

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci

• KIM Jin-Ho

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci

• Kim Dae-hwan

  School Of Electrical Engineering Kookmin University

• Lee Jong

  Inter-univ. Semicon. Res. Center Seoul Nat. Univ.

• Kang Sangwoo

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu

• Kim Jin-Ho

  Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Korea

• Park Il-Han

  Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Korea

• Lee Joung-Eob

  Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Kim Dae-Hwan

  School of Electrical Engineering, Kookmin University, Chongnung-dong, Songbuk-gu, Seoul 146-702, Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

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