Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs(Ultra-Thin Gate Insulators,<Special Section>Fundamentals and Applications of Advanced Semiconductor Devices)

スポンサーリンク

概要

• 論文の詳細を見る

• Accurate extraction of the trap position in the oxide in deep-submicron MOSFET by RTN measurement has been investigated both theoretically and experimentally. The conventional equation based on the ratio of emission time and capture time ignores two effects, that is, the poly gate depletion effect and surface potential variation in strong inversion regime. In this paper, by including both of the two effects, we have derived a new equation which gives us more accurate information of the trap depth from the interface and the trap energy. With experimental result, we compare the trap depth obtained from the new equation and that of the conventional method.

• 社団法人電子情報通信学会の論文
• 2007-05-01

著者

• CHO Seongjae

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• Cho Seongjae

  Inter-university Semiconductor Research Center Seoul National University:school Of Electrical Engine

• Shin Hyungcheol

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci

• LEE Hochul

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci

• YOON Youngchang

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci

• Shin Hyungcheol

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu

• Shin Hyungcheol

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Lee Hochul

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Yoon Youngchang

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Shin Hyungcheol

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat

• Shin Hyungcheol

  Inter-university Semiconductor Research Center (isrc)

• Shin Hyungcheol

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Cho Seongjae

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

関連論文

• Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
• A new cone-type 1T DRAM cell (Electron devices)
• Independent Gate Twin-bit SONOS flash memory with split-gate effect (Silicon devices and materials)
• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
• Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
• Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
• Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
• Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
• 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
• Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
• 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
• Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
• Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
• An Analytic Current-Voltage Equation for Top-contact OTFTs Including the Effects of Variable Series Resistance
• Spatial Distribution of Channel Thermal Noise in Short-Channel MOSFETs
• Low Hysteresis Organic Thin-Film Transistors and Inverters with Hybrid Gate Dielectric
• Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
• Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
• Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
• Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
• Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
• Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
• Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
• 16GHz CMOS LNA design without Source degeneration inductor (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
• 16GHz CMOS LNA design without Source degeneration inductor (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
• Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
• Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
• 3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
• Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
• Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
• FN Stress Induced Degradation on Random Telegraph Signal Noise in Deep Submicron NMOSFETs
• Investigating programming motivation sources from student behavior (教育工学)
• Design and Simulation of Asymmetric MOSFETs(Junction Formation and TFT Reliability,Fundamentals and Applications of Advanced Semiconductor Devices)
• Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs(Ultra-Thin Gate Insulators,Fundamentals and Applications of Advanced Semiconductor Devices)
• Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
• Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
• Design and Simulation of Asymmetric MOSFETs
• Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
• Accurate Extraction of Mobility, Effective Channel Length, and Source/Drain Resistance in 60nm MOSFETs
• RF Linearity Analysis of FinFETs using 3-D Device Simulation (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
• RF Linearity Analysis of FinFETs using 3-D Device Simulation (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
• Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption
• Investigation of Threshold Voltage Disturbance Caused by Programmed Adjacent Cell in Virtual Source/Drain NAND Flash Memory
• Analysis of random telegraph signal noise in dual and single oxide device and its application to complementary metal oxide semiconductor image sensor readout circuit (Special issue: Solid state devices and materials)
• Analysis of Random Telegraph Signal Noise in Dual and Single Oxide Device And Its Application to CMOS Image Sensor Readout Circuit
• FN stess induced degradation on random telegraph signal noise in deep submicron NMOSFETs (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• FN stess induced degradation on random telegraph signal noise in deep submicron NMOSFETs (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Accurate Extraction of the Trap Depth From RTS Noise Data By including Poly Depletion Effect and Surface Potential Variation in MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
• Accurate Extraction of the Trap Depth From RTS Noise Data By including Poly Depletion Effect and Surface Potential Variation in MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
• Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)
• Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)
• Non-Quasi-Static Modeling of Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor and Its Model Verification up to 1 THz
• Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory
• Fin and Recess-Channel Metal Oxide Semiconductor Field Effect Transistor for Sub-50 nm Dynamic Random Access Memory Cell
• Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories
• Room-Temperature Operation of a Single-Electron Transistor Made by Oxidation Process Using the Recessed Channel Structure
• Dual Gate Single-Electron Transistors with a Recessed Channel and Underlapped Source/Drain Structure
• Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor
• Extraction of Interface-States Energy Distribution in Nitrided and Pure Gate Dielectrics for Metal Oxide Semiconductor Field Effect Transistor Applications
• Accurate Extraction of Excess Channel Thermal Noise Coefficient in Berkeley Short-Channel Insulated Gate Field-Effect Transistor Model 4
• Minimization of Gate-Induced Drain Leakage by Controlling Gate Underlap Length for Low-Standby-Power Operation of 20-nm-Level Four-Terminal Silicon-on-Insulator Fin-Shaped Field Effect Transistor
• Dynamic driving current using side gate bias of single-electron transistors
• Extraction of Electron Band Mobility in Amorphous Silicon Thin-Film Transistors
• Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultralow-Power Logic Circuits
• Device and Circuit Codesign Strategy for Application to Low-Noise Amplifier Based on Silicon Nanowire Metal–Oxide–Semiconductor Field Effect Transistors
• A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device
• Electrically Stable Organic Thin-Film Transistors and Circuits Using Organic/Inorganic Double-Layer Insulator
• Self-Aligned Asymmetric Metal–Oxide–Semiconductor Field Effect Transistors Fabricated on Silicon-on-Insulator
• Capacitorless Dynamic Random Access Memory Cell with Highly Scalable Surrounding Gate Structure
• Evaluation and Resolution for Nonideal Characteristics of Complementary Metal–Oxide–Semiconductor Devices Fabricated on Silicon-on-Insulator
• On the Characteristics and Spatial Dependence of Channel Thermal Noise in Nanoscale Metal–Oixde–Semiconductor Field Effect Transistors
• An Analytic Current–Voltage Equation for Top-Contact Organic Thin Film Transistors Including the Effects of Variable Series Resistance
• L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications
• 16GHz CMOS LNA design without Source degeneration inductor (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
• Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs

もっと見る 閉じる

スポンサーリンク