Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption
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概要
- 論文の詳細を見る
Two new NAND structures using double common source line (CSL) and dummy switch and their read operation schemes as a solution for NAND flash memories have been proposed. Compared with conventional scheme, the proposed read schemes improves read disturb characteristics beyond sub-30 nm technology node. By using proposed read scheme, the number of fail bits of proposed NAND was decreased than those of conventional NAND at read cycles. Also, it was proven that they contribute to improve the performance and suppress the power consumption. The proposed NAND was verified by both simulation and experimental measurements in a fabricated 40 nm multi level cell (MLC) NAND device.
- 2011-04-25
著者
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SUH Kang-Deog
Sungkyunkwan University
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Kang Myounggon
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat
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Shin Hyungcheol
Inter-university Semiconductor Research Center (isrc)
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Shin Hyungcheol
Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea
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Lim Youngho
Flash Design Team, Memory Business, Samsung Electronics Co., Ltd., Hwasung 445-701, Korea
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Suh Kang-Deog
Sungkyunkwan University, Suwon 440-746, Korea
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Park Ki-Tae
Flash Design Team, Memory Business, Samsung Electronics Co., Ltd., Hwasung 445-701, Korea
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Song Youngsun
Flash Design Team, Memory Business, Samsung Electronics Co., Ltd., Hwasung 445-701, Korea
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Kang Myounggon
Inter-University Semiconductor Research Center (ISRC)
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Kang Myounggon
Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea
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