Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory

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概要

• 論文の詳細を見る

• A boosted bit line program scheme is proposed for low operating voltage in the multi-level-cell (MLC) NAND flash memory. Our BL to BL boosting scheme, which uses the BL coupling capacitance, is applied to achieve a higher channel potential than is possible with Vcc, so that the Vpass window margin is improved by up to 59% in 40nm MLC NAND flash memory with 2.7V Vcc. In the case of 1.8V Vcc, the margin of the proposed scheme is 12% higher than one of the conventional schemes at 2.7V Vcc.

• （社）電子情報通信学会の論文
• 2010-03-01

著者

• Park Ki-tae

  Samsung Electronics Co. Ltd.

• SONG Youngsun

  Memory Business, Samsung Electronics Co., Ltd.

• PARK Ki-Tae

  Memory Business, Samsung Electronics Co., Ltd.

• KANG Myounggon

  Memory Business, Samsung Electronics Co., Ltd.

• SONG Yunheub

  Hanyang University

• LEE Sungsoo

  Memory Business, Samsung Electronics Co., Ltd.

• LIM Youngho

  Memory Business, Samsung Electronics Co., Ltd.

• SUH Kang-Deog

  Sungkyunkwan University

• KANG Myounggon

  Samsung Electronics Co. Ltd.

• SONG Youngsun

  Samsung Electronics Co. Ltd.

• LEE Sungsoo

  Samsung Electronics Co. Ltd.

• LIM Young-Ho

  Samsung Electronics Co. Ltd.

• Park Ki-tae

  Memory Business Samsung Electronics Co. Ltd.

関連論文

• Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory
• A Low Power and Area Scalable High Voltage Switch Technique for Low Operation Voltage in MLC NAND Flash Memory
• Improving read disturb characteristics by self-boosting read scheme for multilevel NAND flash memories (Special issue: Solid state devices and materials)
• Improving read disturb characteristics by using double common source line and dummy switch architecture in multi level cell NAND flash memory with low power consumption (Special issue: Solid state devices and materials)
• Data Retention Characteristics of MONOS Devices with High-k Dielectrics and High-work Function Metal-gates for Multi-gigabit Flash Memory
• Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption
• Scalable Wordline Shielding Scheme using Dummy Cell beyond 40nm NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell
• Improving Read Disturb Characteristics by Self-Boosting Read Scheme for Multilevel NAND Flash Memories

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