Lee Jong | Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

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概要

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著作論文

A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs)
Pentacene TFTs Fabricated by High-aspect Ratio Metal Shadow Mask
Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
Channel Doping Engineering with Indium as an Alternative p-Type Dopant
Synchronous Mirror Delay for Multi-phase Locking
Synchronous Mirror Delay for Multi-phase Locking
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
Properties of the p^+ poly-Si Gate Fabricated Using the As Preamorphization Method
As Preamorphization of the Predeposited Amorphous Si Layer for the Formation of the Silicided Ultra Shallow p^+-n Junction
Metal FEAs Fabricated with Local Oxidation of Polysilicon for Large-Area Display Applications
Metal FEAs Fabricated with Local Oxidation of Polysilicon for Large-Area Display Applications

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