Yun Jang | Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu

スポンサーリンク

概要

関連著者

もっと見る

著作論文

A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Abnormal Oxidation of Nickel Silicide on N-Type Substrate and Effect of Preamorphization Implantation
Low Temperature Formation of Highly Thermal Immune Ni Germanosilicide Using NiPt Alloy with Co Over-layer in Si_Ge_x according to Different Ge Fractions (x)
Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
Highly Thermal Immune Ni GermanoSilicide with Nitrogen-Doped Ni and Co/TiN Double Capping Layer for Nano-Scale CMOS Applications
Thermally Robust Nickel Silicide Process for Nano-Scale CMOS Technology(Si Devices and Processes, Fundamental and Application of Advanced Semiconductor Devices)
Novel Nitrogen doped Ni SALICIDE Process for Nano-Scale CMOS Technology
Thermally Robust Nickel Silicide Process Technology for Nano-Scale CMOS Technology(Session B5 Si-Devices I)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
Thermally Robust Nickel Silicide Process Technology for Nano-Scale CMOS Technology(Session B5 Si-Devices I)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
Thermally Robust Nickel Silicide Process Technology for Nano-Scale CMOS Technology
Study of Abnormal Oxidation of Ni-Germanosilicide by High Temperature Post-Silicidation Annealing(Session A3 Si Materails and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
Study of Abnormal Oxidation of Ni-Germanosilicide by High Temperature Post-Silicidation Annealing(Session A3 Si Materails and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
Extended word-Line NAND flash memory
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
Design and Simulation of Asymmetric MOSFETs(Junction Formation and TFT Reliability,Fundamentals and Applications of Advanced Semiconductor Devices)
Novel Gate-All-Around MOSFETs with Self-Aligned Structure
Multi-Functionality of Novel Structured Tunneling Devices
Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
Design and Simulation of Asymmetric MOSFETs
4-bit FinFET SONOS flash memory: Optimization of structure and 3D numerical simulation (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
4-bit FinFET SONOS flash memory: Optimization of structure and 3D numerical simulation (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))

もっと見る

スポンサーリンク