Lee Jung | Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

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著作論文

Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
Investigation of Threshold Voltage Disturbance Caused by Programmed Adjacent Cell in Virtual Source/Drain NAND Flash Memory
Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory
Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories
Silicon-Based Dual-Gate Single-Electron Transistors for Logic Applications
Device and Circuit Codesign Strategy for Application to Low-Noise Amplifier Based on Silicon Nanowire Metal–Oxide–Semiconductor Field Effect Transistors
Evaluation and Resolution for Nonideal Characteristics of Complementary Metal–Oxide–Semiconductor Devices Fabricated on Silicon-on-Insulator

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