Kang Sangwoo | Inter-university Semiconductor Research Center Seoul National University:school Of Electrical Engine
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概要
- 同名の論文著者
- Inter-university Semiconductor Research Center Seoul National University:school Of Electrical Engineの論文著者
関連著者
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Kang Sangwoo
Seoul National Univ. Seoul Kor
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Kang Sangwoo
Inter-university Semiconductor Research Center Seoul National University:school Of Electrical Engine
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Sim Jae
Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U
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PARK Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu
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Park Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea
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Park Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea
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LEE Jong
Inter-University Semiconductor Research Center, Seoul National University
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Lee J
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
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Lee Jong
Inter-univ. Semicon. Res. Center Seoul Nat. Univ.
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Kang Sangwoo
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
著作論文
- Nanoscale Multi-Line Patterning Using Sidewall Structure
- Single-Electron MOS Memory with a Defined Quantum Dot Based on Conventional VLSI Technology
- Single-Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
- Single Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
- Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs)
- Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure
- Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
- Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)