Kang Sangwoo | Inter-university Semiconductor Research Center Seoul National University:school Of Electrical Engine

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著作論文

Nanoscale Multi-Line Patterning Using Sidewall Structure
Single-Electron MOS Memory with a Defined Quantum Dot Based on Conventional VLSI Technology
Single-Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
Single Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs)
Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
Nanoscale Poly-Si Line Formation and Its Uniformity
Nanoscale Poly-Si Line Formation and Its Uniformity
Design and Simulation of Asymmetric MOSFETs(Junction Formation and TFT Reliability,Fundamentals and Applications of Advanced Semiconductor Devices)
Novel Gate-All-Around MOSFETs with Self-Aligned Structure
Nanoscale Poly-Si Line Formation and Its Uniformity (2001 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices(AWAD 2001))
Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
Design and Simulation of Asymmetric MOSFETs
70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As_2^+ Å Low Energy Ion Implantations
Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))

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