Active Channel Reservation for Coexistence Mechanism (ACROS) for IEEE 802.15.4 and IEEE 802.11
スポンサーリンク
概要
- 論文の詳細を見る
- 2010-08-01
著者
-
Park Hong
Kangwon National Univ. Kor
-
Park Hong
The Faculty Of Electrical Eng. Kangwon National University
-
LEE Jong
School of Electrical Engineering, Seoul National University
-
Lee Jong
School Of Adv. Mat. Sci. & Eng. Sungkyunkwan Univ.
-
Kwon Wook
School Of Electrical Eng. & Computer Sci. Seoul Nat'l Univ.
-
Kwon Wook
Eecs Seoul National University
-
Kwon Wook
School Of Electrical Engineering Seoul National University
-
Lee Jong
School Of Electrical Engineering Seoul National University
-
Park Hong
Electrical Eng. Of Kangwon National University
-
Woo Dong
School Of Electrical And Computer Engineering Georgia Institute Of Technology
-
Shin Soo
Wimax Design Lab. In Samsung Electronics
関連論文
- 2P4-3 横振動により接合された高延性ENIGめっき電極の評価(ポスターセッション)
- Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
- Spatial Distribution of Channel Thermal Noise in Short-Channel MOSFETs
- Improving the Cell Characteristics Using SiN Liner at Active Edge in 4G NAND Flash
- Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Packet Error Rate Analysis of IEEE802.15.4 under Saturated IEEE802.11b Network Interference(Network)
- Fuzzy Logic-Based Quantized Event Filter for RFID Data Processing
- Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process
- Throughput and Optimal ATIM Window of IEEE802.11 Distributed Coordination Function in Power Saving Mode(Network)
- Control of the Microstructure of (Pb, La) TiO_3 Thin Films by Metal-Organic Chemical Vapor Deposition Using a Solid Delivery System for Ferroelectric Domain Memory
- Synchronous Mirror Delay for Multi-phase Locking
- Synchronous Mirror Delay for Multi-phase Locking
- Degradation and Recovery Phenomena of Thin Gate Oxide Films under Dynamic Negative-Bias Temperature Instability (NBTI) Stress (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- Degradation and Recovery Phenomena of Thin Gate Oxide Films under Dynamic Negative-Bias Temperature Instability (NBTI) Stress (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- Isolation of 151 Mutants that Have Developmental Defects from T-DNA Tagging
- Anomalous Noise Degradation Caused by Device Size Effects in SOI MOSFETs
- On the Bit Error Probability of 16DAPSK in a Frequency-Selective Fast Rayleigh Fading Channel with Cochannel Interference
- Active Channel Reservation for Coexistence Mechanism (ACROS) for IEEE 802.15.4 and IEEE 802.11
- Dependence of Contact Resistance on Substrate Doping and Impact of Mixed Ion Implantation
- Lateral Silicon Field-Emission Devices using EIectron Beam Lithography
- Monte Carlo Simulation of Single-Electron Nanocrystal Memories
- Performance Analysis of the Exhaustive Token-Controlled Network with Finite Buffers
- Non-Quasi-Static Small-Signal Model of RF MOSFETs Valid up to 110GHz
- New Recursive Least Squares Algorithms without Using the Initial Information
- On State Avoidance Policies for Non-Ordinary Controlled Petri Nets with Uncontrollable Transitions
- CARS temperature measurement in a Liquid Kerosene fueled Gas Turbine Combustor Sector Rigs(Measurement, Temperature)
- Generalizing the Hadamard Matrix Using the Reverse Jacket Matrix(Digital Signal Processing)
- Performance Analysis of the IEEE 802.11 DCF with Time-Varying Channel Environments(Wireless Communication Technologies)
- An advanced method for the determination of carboxyl methyl esterase activity using gas chromatography-chemical ionization-mass spectrometry
- Stability-Guaranteed Horizon Size for Receding Horizon Control(Systems and Control)
- Extraction of Vertical, Lateral Locations and Energies of Hot-Electrons-Induced Traps through the Random Telegraph Noise
- Improving the Cell Characteristics Using SiN Liner at Active Edge in 4 Gbits NAND Flash Memories
- Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process
- Monte Carlo Simulation of Single-Electron Nanocrystal Memories
- Highly Manufacturable and Reliable 80-nm Gate Twin Silicon–Oxide–Nitride–Oxide–Silicon Memory Transistor
- Characterization of Sensitivity and Resolution of Silicon Resistive Probe