Characterization of Sensitivity and Resolution of Silicon Resistive Probe

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概要

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• The resistive probe, which can detect the variation in probe resistance while scanning over positive/negative biased bits, has been considered as the one of the most suitable candidate for used as a high-speed, ultralarge-storage systems. Ultralarge-storage density has been demonstrated by the electrical recording technique in which surface charge is read in ferroelectric materials, which is named as scanning resistive probe microscopy (SRPM). Because of the difficulty of fabricating, the SRPM device little has been previously done on relating probe properties with process parameters. As it is important in probe design to analyze the properties of sensitivity and resolution for different process and device parameters, the parameters of the fabricated microscope are embedded in the simulation performed in this study. To obtain the optimum resistive probe design, we analyze the effect of different process parameters on the properties. In the first part of the paper, the device structure fabricated to identify the electrostatic charge effects between the tip and the poly silicon domain (surface) is presented. In the second part, we explain the process conditions of the resistive probe. In the third part, we present the sensitivity and resolution for different process conditions. The probe is placed in contact with a poly silicon domain (surface) to measure the field sensitivity, and a 0.3% resistance change per voltage applied to the surface is detected with a spatial resolution of less than 1000 nm. The sensitivity and resolution for different implantation doses, wet oxidation time, and resistances in the high-doped n-type region are also presented. We found that there is a correlation between sensitivity and resolution for different implantation doses and annealing times. Although the sensitivity decreases as resistance increases, the change is less than 10% even at a resistance of 200 $\Omega$. Therefore, the resistance of the cantilever can be neglected in our study of probe sensitivity.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2008-03-25

著者

• Lee Jong

  School Of Adv. Mat. Sci. & Eng. Sungkyunkwan Univ.

• Song Ickhyun

  School Of Electrical Engineering And Computer Science Seoul National University

• Shin Hyungcheol

  School Of Electrical Engineering And Computer Science Seoul National University

• Min Dong-Ki

  Semiconductor Device and Material Laboratory, Samsung Advanced Institute of Technology, Mt. 14-1, Nongseo-ri, Kiheung-eup, Yongin, Gyunggi 449-712, Korea

• Park Byung-Gook

  School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Korea

• Park Byung-Gook

  School of Electrical Engineering & Inter-University Semiconductor Research Center (ISRC), Seoul National University, Shilim-Dong, Kwanak-Gu, Seoul 151-742, Republic of Korea

• Kim Junsoo

  School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Korea

• Lee Jaehong

  School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Korea

• Lee Jong

  School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Korea

• Hong Seungbum

  Semiconductor Device and Material Laboratory, Samsung Advanced Institute of Technology, Mt. 14-1, Nongseo-ri, Kiheung-eup, Yongin, Gyunggi 449-712, Korea

• Ko Hyoungsoo

  Semiconductor Device and Material Laboratory, Samsung Advanced Institute of Technology, Mt. 14-1, Nongseo-ri, Kiheung-eup, Yongin, Gyunggi 449-712, Korea

• Park Hongsik

  Semiconductor Device and Material Laboratory, Samsung Advanced Institute of Technology, Mt. 14-1, Nongseo-ri, Kiheung-eup, Yongin, Gyunggi 449-712, Korea

• Park Chulmin

  Semiconductor Device and Material Laboratory, Samsung Advanced Institute of Technology, Mt. 14-1, Nongseo-ri, Kiheung-eup, Yongin, Gyunggi 449-712, Korea

• Jung Juhwan

  Semiconductor Device and Material Laboratory, Samsung Advanced Institute of Technology, Mt. 14-1, Nongseo-ri, Kiheung-eup, Yongin, Gyunggi 449-712, Korea

• Shin Hyungcheol

  School of Electrical Eng.

• Park Byung-Gook

  School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea

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