Low cost CMOS LNA design using thin-metal CMOS process (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))

スポンサーリンク

概要

• 論文の詳細を見る

• This paper presents the design and measurement results of cost-effective CMOS Low Noise Amplifier (LNA) for high frequency application. For low cost design, this circuit has been fabricated with a 0.18μm thin metal CMOS process which the top metal thickness is only 0.84μm. To obtain the high-quality factor inductor in LNA design, patterned-ground shields (PGS) are placed. Moreover, to eliminate additional noise source from the substrate resistive components of RF interconnects, MIM capacitor, RF-pad and grounded metal-1 were placed underneath them. The LNA achieves power gain of 15.6dB, noise figure of 3.5dB at 2.8GHz at 6.88mW power dissipation for a 1.6V power supply. It occupies a whole circuit area of 1.2mm^2.

• 社団法人電子情報通信学会の論文
• 2007-06-18

著者

• SONG Ickhyun

  Inter-University Semiconductor Research Center (ISRC) and School of EE, Seoul National University

• Yoon Yeo-nam

  Dept. Of Electrical Engineering And Computer Science Seoul National University

• Song Ickhyun

  School Of Electrical Engineering And Computer Science Seoul National University

• Song Ickhyun

  Inter-university Semiconductor Research Center (isrc):school Of Electrical Engineering Seoul Nationa

• Song Ickhyun

  Dept. Of Eecs Seoul National University

• Jhon Hee-sauk

  School Of Electrical Engineering And Computer Science Seoul National University

• Jhon Hee-Sauk

  Dept. of Electrical Engineering and Computer Science, Seoul National University

• Shin Hyungcheol

  Dept. of Electrical Engineering and Computer Science, Seoul National University

• Shin Hyungcheol

  School Of Electrical Engineering And Computer Science Seoul National University

• Shin Hyungcheol

  Dept. Of Eecs Seoul National University

• Shin Hyungcheol

  Dept. Of Eecs Kaist

関連論文

• 24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices)
• Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
• Spatial Distribution of Channel Thermal Noise in Short-Channel MOSFETs
• Improving the Cell Characteristics Using SiN Liner at Active Edge in 4G NAND Flash
• Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
• FN Stress Induced Degradation on Random Telegraph Signal Noise in Deep Submicron NMOSFETs
• Low cost CMOS LNA design using thin-metal CMOS process (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Low cost CMOS LNA design using thin-metal CMOS process (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• 24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices)
• Non-Quasi-Static Small-Signal Model of RF MOSFETs Valid up to 110GHz
• Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)
• Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)
• ED2000-80 / SDM2000-80 MOS Memory Using Si Nanocrystals Formed by Wet Etching of Poly-Silicon Along Grain Boundaries
• CMOS low-noise amplifer with noise suppression technique from gate resistance (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• CMOS low-noise amplifer with noise suppression technique from gate resistance (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Extraction of Vertical, Lateral Locations and Energies of Hot-Electrons-Induced Traps through the Random Telegraph Noise
• Improving the Cell Characteristics Using SiN Liner at Active Edge in 4 Gbits NAND Flash Memories
• Simple Wide-Band Metal-Insulator-Metal (MIM) Capacitor Model for RF Applications and Effect of Substrate Grounded Shields
• Highly Manufacturable and Reliable 80-nm Gate Twin Silicon–Oxide–Nitride–Oxide–Silicon Memory Transistor
• Simultaneous Extraction of Locations and Energies of Two Independent Traps in Gate Oxide From Four-Level Random Telegraph Signal Noise
• Characterization of Sensitivity and Resolution of Silicon Resistive Probe

もっと見る 閉じる

スポンサーリンク