Efficient Timing Verification of Latch-Synchronized Systems

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概要

• 論文の詳細を見る

• This paper presents an event-driven approach to the timing verification of latch-synchronized systems. The proposed method performs critical path extraction and timing error detection at the same time, and extracts the critical path only if necessary. By doing so, the complexity of analysis is reduced and efficiency is greatly improved over the conventional approaches which detect timing errors after extracting the complete critical paths of the system. Experimental results show that, compared to the existing methods, it provides a more than 12-fold improvement in speed on the average for ISCAS benchmark circuits, and the relative efficiency of analysis improves as the circuit size grows.

• 社団法人電子情報通信学会の論文
• 1997-09-25

著者

• Kim Young

  The Department Of Electronic Engineering Konkuk University

• Kim Young

  Applied Physics Group Korea Institute Of Science And Technology

• Kim Y

  Korea Basic Sci. Inst. Daejeon Kor

• HAN Sang-Yeol

  the Department of Electronic and Electrical Engineering, Pohang University of Science and Technology

• Han Sang-yeol

  The Department Of Electronic And Electrical Engineering Pohang University Of Science And Technology

• KIM Young

  the Department of Electronic and Electrical Engineering, Pohang University of Science and Technology

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