Analytical Modeling of Realistic Single-Electron Transistors Based on Metal-Oxide-Semiconductor Structure with a Unique Distribution Function in the Coulomb-Blockade Oscillation Region
スポンサーリンク
概要
- 論文の詳細を見る
Novel metal-oxide-semiconductor (MOS)-based single-electron transistors (MOSETs) using band-to-band tunneling mechanism have been fabricated by the conventional silicon-on-insulator (SOI) MOSFET technologies. The fabricated SETs have tunnel barriers and quantum-dot formed by an extremely small channel between two p+-n+ tunnel junctions in the degenerately doped SOI MOSFET. Coulomb oscillation was observed in the subthreshold region at liquid nitrogen temperature and total capacitance of quantum-dot is 2.25 aF which is well matched to the device geometry. In order to validate the operation principle of our device, we have implemented an analytical device model in the simulation program with integrated circuit emphasis (SPICE). SPICE simulation of our model with a unique distribution function has reproduced the experimental results with good agreement for wide gate and drain bias range.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2004-04-15
著者
-
KIM Dae
Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National
-
Baek Gwanghyeon
Inter-university Semiconductor Research Center School Of Electrical Engineering Seoul National Unive
-
Lee Jong
Inter-univ. Semicon. Res. Center Seoul Nat. Univ.
-
Song Ki-whan
Inter-university Semiconductor Research Center School Of Electrical Engineering Seoul Nat'l Uni
-
Huh Jung
Inter-university Semiconductor Research Center School Of Electrical Engineering Seoul Nat'l Uni
-
Kim Kyung
Inter-university Semiconductor Research Center School Of Electrical Engineering Seoul Nat'l Uni
-
Song Ki-Whan
Inter-University Semiconductor Research Center, School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-ku, Seoul 151-742, Korea
-
Huh Jung
Inter-University Semiconductor Research Center, School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-ku, Seoul 151-742, Korea
-
Kim Hyun
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science (EECS), Seoul National University, Seoul 151-742, Korea
-
Park Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea
-
Park Byung-Gook
Inter-University Semiconductor Research Center, School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-ku, Seoul 151-742, Korea
-
Baek Gwanghyeon
Inter-University Semiconductor Research Center, School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-ku, Seoul 151-742, Korea
-
Kim Hyun
Inter-University Semiconductor Research Center, School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-ku, Seoul 151-742, Korea
-
Park Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea
関連論文
- Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
- Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
- Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
- A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
- A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
- Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
- Nanoscale Multi-Line Patterning Using Sidewall Structure
- Single-Electron MOS Memory with a Defined Quantum Dot Based on Conventional VLSI Technology
- Single-Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
- Single Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
- Single Electron Memory with a Defined Poly-Si Dot Based on Conventional VLSI Technology
- Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and Its Modeling
- Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and Its Modeling
- Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
- Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
- Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
- Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
- Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
- Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
- Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
- 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
- Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
- Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
- 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
- Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs)
- An Analytic Current-Voltage Equation for Top-contact OTFTs Including the Effects of Variable Series Resistance
- Low Hysteresis Organic Thin-Film Transistors and Inverters with Hybrid Gate Dielectric
- Pentacene TFTs Fabricated by High-aspect Ratio Metal Shadow Mask
- Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
- Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
- Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
- Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
- Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
- Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
- Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
- Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
- Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure
- Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
- Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
- Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
- Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
- Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
- Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
- 3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
- Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
- Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
- Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
- Full-swing pentacene organic inverter with long-channel driver and short-channel load
- A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology
- Silicon Quantum Tunneling Devices - FIBTET and MOSET
- Analytical Modeling of Realistic Single-Electron Transistors Based on Metal-Oxide-Semiconductor Structure with a Unique Distribution Function in the Coulomb-Blockade Oscillation Region
- Indium Doped nMOSFETs and Buried Channel pMOSFETs with n^+ Polysilicon Gate
- Channel Doping Engineering with Indium as an Alternative p-Type Dopant
- Nanoscale Poly-Si Line Formation and Its Uniformity
- Nanoscale Poly-Si Line Formation and Its Uniformity
- Design and Simulation of Asymmetric MOSFETs(Junction Formation and TFT Reliability,Fundamentals and Applications of Advanced Semiconductor Devices)
- Novel Gate-All-Around MOSFETs with Self-Aligned Structure
- Multi-Functionality of Novel Structured Tunneling Devices
- Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
- Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
- Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
- Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
- Design and Simulation of Asymmetric MOSFETs
- Integration Process of Impact-Ionization Metal-Oxide-Semiconductor Devices with Tunneling Field-Effect-Transistors and Metal-Oxide-Semiconductor Field-Effect Transistors
- Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
- Side-Gate Design for 50nm Electrically Induced Source/Drain MOSFETs
- Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
- 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As^+_2 Low Energy Implantations
- 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As_2^+ Å Low Energy Ion Implantations
- Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
- Properties of the p^+ poly-Si Gate Fabricated Using the As Preamorphization Method
- Metal FEAs Fabricated with Local Oxidation of Polysilicon for Large-Area Display Applications
- Metal FEAs Fabricated with Local Oxidation of Polysilicon for Large-Area Display Applications
- Ultra Shallow p+n Junction Formation Using the Solid Phase Diffusion(SPD) through'a-Si/Thin Barrier Oxide' Layer
- Extended Word-Line NAND Flash Memory
- A New Recessed Channel Metal-Oxide-Semiconductor Field-Effect Transistor with Selectively Halo-Doped Channel and Deep Graded Source/Drain
- Self-Aligned Dual-Gate Single-Electron Transistors
- Study on Threshold Voltage Control of Tunnel Field-Effect Transistors Using VT-Control Doping Region
- Design Guideline of Si-Based L-Shaped Tunneling Field-Effect Transistors
- Comparative Study on Top- and Bottom-Source Vertical-Channel Tunnel Field-Effect Transistors
- Study on Threshold Voltage Control of Tunnel Field-Effect Transistors Using V_T-Control Doping Region
- Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultralow-Power Logic Circuits
- Stable Extraction of Threshold Voltage Using Transconductance Change Method for CMOS Modeling, Simulation and Characterization
- Electrically Stable Organic Thin-Film Transistors and Circuits Using Organic/Inorganic Double-Layer Insulator
- Self-Aligned Asymmetric Metal–Oxide–Semiconductor Field Effect Transistors Fabricated on Silicon-on-Insulator
- Capacitorless Dynamic Random Access Memory Cell with Highly Scalable Surrounding Gate Structure
- Full-Swing Pentacene Organic Inverter with Long-Channel Driver and Short-Channel Load
- Analytical Modeling of Realistic Single-Electron Transistors Based on Metal-Oxide-Semiconductor Structure with a Unique Distribution Function in the Coulomb-Blockade Oscillation Region
- Evaluation and Resolution for Nonideal Characteristics of Complementary Metal–Oxide–Semiconductor Devices Fabricated on Silicon-on-Insulator
- Novel Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors with Self-Aligned Structure
- Novel Tunneling Devices with Multi-Functionality
- On the Characteristics and Spatial Dependence of Channel Thermal Noise in Nanoscale Metal–Oixde–Semiconductor Field Effect Transistors
- An Analytic Current–Voltage Equation for Top-Contact Organic Thin Film Transistors Including the Effects of Variable Series Resistance
- L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications
- Complementary-Metal--Oxide--Semiconductor Technology-Compatible Tunneling Field-Effect Transistors with 14 nm Gate, Sigma-Shape Source, and Recessed Channel