Complementary-Metal--Oxide--Semiconductor Technology-Compatible Tunneling Field-Effect Transistors with 14 nm Gate, Sigma-Shape Source, and Recessed Channel

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概要

• 論文の詳細を見る

• A new design of tunneling field-effect transistor (TFET) focusing on the compatibility to the current Si complementary-metal--oxide--semiconductor (CMOS) technology is proposed. In addition to use of the structural components of the state-of-the-art CMOS technologies, such as \Sigma-shaped embedded SiGe and the replacement gate techniques, two-step sidewall image transfer gate-patterning and channel recess process are adopted to form highly-scaled nanoscale TFET. Process integration scheme and the expected device characteristics are examined on the basis of technology computer-aided design (TCAD) simulation on 14-nm-gate model devices. Tunability of transfer characteristics with doping around tip region, control of short-channel effect with channel recess, and improvement of current drivaility with SiGe composition are studied. Design of the source region is found to be critical in controlling the current drivability of the device and output characteristics.

• 2013-06-25

著者

• Kim Sang

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu

• Kim Hyun

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science (EECS), Seoul National University, Seoul 151-742, Korea

• KIM Hyungjin

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University

• Sun Min-Chul

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science (EECS), Seoul National University, Seoul 151-742, Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

関連論文

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