Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)
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概要
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We propose a new three-dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) [1]. Channels are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked channels, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed.
著者
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Kim Wandong
Inter-university Semiconductor Research Center
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Kim Yoon
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu
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Park Se
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Computer Science Seoul National University
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Seo Joo
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Computer Science Seoul National University
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Kim Wandong
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University
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KIM Hyungjin
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University
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Park Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea
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