High Speed, Low Power Programming in 0.17μm Channel Length NOR-type Floating Gate Flash Memory Cell Free of Drain Turn-On Effects

概要

論文の詳細を見る
We present a fast low power programming in floating gate electrically erasable and programmable read only memory (EEPROM) cells with the aspect ratio of 0.09 / 0.17 μm. The threshold voltage shift ($\Delta V_{\text{TH}}$) of 5V, for example, was done in less than 1 μs, using the peak drain current ($I_{\text{D}}$) of ${\approx}100$ μA. More importantly, by using the substrate bias ($V_{\text{B}}$), programming was done in 2–3 μs at $I_{\text{D}}$ of 30 μA and $V_{\text{D}}$ of 3V. This observed speed is faster than reported values by about 2.5 and power used was about 50% lower than the previous one. The optimal programming bias conditions are presented, together with the reasons for fast programming.
Japan Society of Applied Physicsの論文
2004-02-01