Highly Reliable 256Mb NOR Flash MLC with Self-Aligned Process and Controlled Edge Profile
スポンサーリンク
概要
- 論文の詳細を見る
- 2005-09-13
著者
-
KIM Dae
Korea institute for Advanced Study
-
Kim Kinam
Advanced Technology Development 2 Team Semiconductor R&d Center Memory Division Samsung Electron
-
Kim Kinam
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kim Kinam
Advanced Technology Development 2 Memory Device Business Samsung Electronics Co.
-
Park Chan-kwang
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Han Jee
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
HAN Jung
Advanced Technology Development Team2, Semiconductor R&D Center, Samsung Electronics Co., LTD.
-
LEE Heon
Advanced Technology Development Team2, Semiconductor R&D Center, Samsung Electronics Co., LTD.
-
SIM Sang-Pil
Advanced Technology Development Team2, Semiconductor R&D Center, Samsung Electronics Co., LTD.
-
KWON Wook
Advanced Technology Development Team, Semiconductor R&D Center, Samsung Electronics Co., LTD.
-
KIM Bomsoo
Korea Institute for Advanced Study
-
BAEK Chang-Ki
Korea Institute for Advanced Study
-
LEE Wook
Advanced Technology Development Team, Semiconductor R&D Center, Samsung Electronics Co., LTD.
-
JUNG Cheol
Advanced Technology Development Team, Semiconductor R&D Center, Samsung Electronics Co., LTD.
-
JANG Young
Advanced Technology Development Team, Semiconductor R&D Center, Samsung Electronics Co., LTD.
-
PARK Jeung
Advanced Technology Development Team, Semiconductor R&D Center, Samsung Electronics Co., LTD.
-
Han Jung
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kwon Wook
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Jung Cheol
Advanced Technology Development Team Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Park Jeung
Advanced Technology Development Team Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Sim Sang-pil
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kwon Wook-hyun
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kim Dae
Korea Atomic Energy Research Institute
-
Lee Heon
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Jang Young
Advanced Technology Development Team Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Lee Wook
Advanced Technology Development Team Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kwon Wook
Advanced Technology Development Team 2, Semiconductor R&D Center, Samsung Electronics Co., Ltd., San #24 Nongseo-dong, Giheung-gu, Yongin, Gyeonggi-do 446-711, Korea
-
Park Chan-Kwang
Advanced Technology Development Team 2, Semiconductor R&D Center, Samsung Electronics Co., Ltd., San #24 Nongseo-dong, Giheung-gu, Yongin, Gyeonggi 446-711, Korea
関連論文
- A New Quantum Effect in Metal-Oxide-Semiconductor Field-Effect Transistor : Threshold Voltage Creep with Gate Voltage
- High Density and Ultra-Low Power Mobile SRAM Using the Novel Double S^3 (Stacked Single-crystal Silicon) Technology and KrF lithography
- Self-Aligned Local Channel Implantation Using Reverse Gate Pattern for Deep Submicron Dynamic Random Access Memory Cell Transistors
- Cell Transistor Design Using Self-Aligned Local Channel Implant(SALCI) for 4Gb DRAMs and Beyond
- Tunnel Oxide Optimization to Improve Post-Cycling Retention of Flash Memories
- Highly Reliable 256Mb NOR Flash MLC with Self-Aligned Process and Controlled Edge Profile
- Ge_2Sb_2Te_5 Confined Structures and Integration of 64Mb Phase-Change Random Access Memory
- Optimization of Ring Type Electrode Process for High Density PRAM
- Near Surface Oxide Trap Density Profiling in NO and Remote Plasma Nitrided Oxides in Nano-Scale MOSFETs, Using Multi-Temperature Charge Pumping Technique : N_ vs. Oxide Processing
- The impact of RTS on the Vt variation of 65nm MLC NOR flash memory
- Novel Capacitor Structure Using Sidewall Spacer for Highly Reliable Ferroelectric Random Access Memory Device
- Robust Three-Metallization Back End of Line Process for 0.18μm Embedded Ferroelectric Random Access Memory
- High Density (256Mb and Beyond) PRAM Integration Using 3-D Cell Array Transistors(Plenary Session,AWAD2006)
- High Density (256Mb and Beyond) PRAM Integration Using 3-D Cell Array Transistors(Plenary Session,AWAD2006)
- Highly Reliable Ring Type Contact Scheme for High Density PRAM
- Design Technique for Ramped Gate Soft-Programming in Over-Erased NOR Type Flash EEPROM Cells
- High Speed, Low Power Programming in 0.17μm Channel Length NOR-type Floating Gate Flash Memory Cell Free of Drain Turn-On Effects
- Simple Experimental Determination of the Spread of Trapped Hot Holes Injected in Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Cells : Optimized Erase and Cell Shrinkage
- Spatial and Temporal Characterization of Programming Charge in SONOS Memory Cell : Effects of Localized Electron Trapping
- Robust 2-D Stack Capacitor Technologies for 64Mb 1T1C FRAM
- GST Confined Structure and Integration of 64Mb PRAM
- Robust 3-Metallization BEOL Process for 0.18μm Embedded FRAM
- Integration and Electrical Properties of Novel Ferroelectric Capacitors for 0.25μm 1 Transistor 1 Capacitor Ferroelectric Random Access Memory (1T1C FRAM)
- Novel Capacitor Technology for Sub-Quarter Micron 1T1C FRAM
- Invited Integration Technologies for High Density Emerging New Memories (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- Invited Integration Technologies for High Density Emerging New Memories (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- ICONE11-36500 SHAPE OPTIMIZATION OF SPACER GRID SPRINGS TO SUPPORT NUCLEAR FUEL RODS
- Highly Manufacturable 64M bit Ultra Low Power SRAM Using a Novel 3-Dimensional S^3 (Stacked Single-crystal Si) Cell Technology
- The Impact of Random Telegraph Signals on the Threshold Voltage Variation of 65 nm Multilevel NOR Flash Memory
- Robust Two-Dimensional Stack Capacitor Technologies for 64 Mbit One-Transistor–One-Capacitor Ferroelectric Random Access Memory
- Ring Contact Electrode Process for High Density Phase Change Random Access Memory
- Highly Reliable Ring-Type Contact for High-Density Phase Change Memory
- High Density FRAM Technology
- MRAM's future prospects and its challenges
- High Density (256Mb and Beyond) PRAM Integration Using 3-D Cell Array Transistors
- Ge2Sb2Te5 Confined Structures and Integration of 64 Mb Phase-Change Random Access Memory
- A Novel Structure for Beyond-45 nm NOR Flash Technology Featuring Short Channel Effect Immunity and Low Random Telegraph Signal Noise
- Invited The prospective on New Emerging Memories (FRAM, MRAM, PRAM) in nano era (先端デバイスの基礎と応用に関するアジアワークショップ)
- [Invited] The Prospective on New Emerging Memories (FRAM, MRAM, PRAM) in nano era (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
- Robust Three-Metallization Back End of Line Process for 0.18 μm Embedded Ferroelectric Random Access Memory
- Novel Capacitor Structure Using Sidewall Spacer for Highly Reliable Ferroelectric Random Access Memory Device
- Comparison of Series Resistance and Mobility Degradation Extracted from n- and p-Type Si-Nanowire Field Effect Transistors Using the $Y$-Function Technique
- A Novel Body-Tied Fin Field Effect Transistor Flash Memory Structure with $\lambda$-Shaped Floating Gate for Sub 45 nm NOR Flash Memory
- Design Technique for Ramped Gate Soft-Programming in Over-Erased NOR Type Flash EEPROM Cells
- Current Development Status and Future Challenges of Ferroelectric Random Access Memory Technologies
- Spatial and Temporal Characterization of Programming Charge in SONOS Memory Cell: Effects of Localized Electron Trapping
- High Speed, Low Power Programming in 0.17μm Channel Length NOR-type Floating Gate Flash Memory Cell Free of Drain Turn-On Effects
- Erratum: "A Novel Body-Tied Fin Field Effect Transistor Flash Memory Structure with $\lambda$-Shaped Floating Gate for Sub 45 nm NOR Flash Memory"