The impact of RTS on the Vt variation of 65nm MLC NOR flash memory
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概要
- 論文の詳細を見る
- 2007-09-19
著者
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Park Chan-kwang
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
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KWON Wook-Hyun
Advanced Technology Development Team2, Semiconductor R&D Center, Samsung Electronics Co., LTD.
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HAN Jung
Advanced Technology Development Team2, Semiconductor R&D Center, Samsung Electronics Co., LTD.
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LEE Bong
Advanced Technology Development Team2, Semiconductor R&D Center, Samsung Electronics Co., LTD.
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Han Jung
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
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Kwon Wook
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
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Kwon Wook-hyun
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
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CAI Yimao
Advanced Technology Development Team2, Semiconductor R&D Center, Samsung Electronics Co., LTD.
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HEUB Song
Advanced Technology Development Team2, Semiconductor R&D Center, Samsung Electronics Co., LTD.
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Lee Bong
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
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Heub Song
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
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Cai Yimao
Advanced Technology Development Team2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
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Lee Bong
Advanced Technology Development Team 2, Semiconductor R&D Center, Samsung Electronics Co., Ltd., San #24 Nongseo-dong, Giheung-gu, Yongin, Gyeonggi 446-711, Korea
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Kwon Wook-Hyun
Advanced Technology Development Team 2, Semiconductor R&D Center, Samsung Electronics Co., Ltd., San #24 Nongseo-dong, Giheung-gu, Yongin, Gyeonggi 446-711, Korea
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Park Chan-Kwang
Advanced Technology Development Team 2, Semiconductor R&D Center, Samsung Electronics Co., Ltd., San #24 Nongseo-dong, Giheung-gu, Yongin, Gyeonggi 446-711, Korea
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Cai Yimao
Advanced Technology Development Team 2, Semiconductor R&D Center, Samsung Electronics Co., Ltd., San #24 Nongseo-dong, Giheung-gu, Yongin, Gyeonggi 446-711, Korea
関連論文
- Tunnel Oxide Optimization to Improve Post-Cycling Retention of Flash Memories
- Highly Reliable 256Mb NOR Flash MLC with Self-Aligned Process and Controlled Edge Profile
- The impact of RTS on the Vt variation of 65nm MLC NOR flash memory
- The Impact of Random Telegraph Signals on the Threshold Voltage Variation of 65 nm Multilevel NOR Flash Memory
- A Novel Structure for Beyond-45 nm NOR Flash Technology Featuring Short Channel Effect Immunity and Low Random Telegraph Signal Noise
- A Novel Body-Tied Fin Field Effect Transistor Flash Memory Structure with $\lambda$-Shaped Floating Gate for Sub 45 nm NOR Flash Memory
- Erratum: "A Novel Body-Tied Fin Field Effect Transistor Flash Memory Structure with $\lambda$-Shaped Floating Gate for Sub 45 nm NOR Flash Memory"