Design Technique for Ramped Gate Soft-Programming in Over-Erased NOR Type Flash EEPROM Cells
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概要
- 論文の詳細を見る
We present an efficient design technique for implementing the optimal ramped gate soft-programming for curing the over-erased flash EEPROM cells. The technique does not rely on any $I$–$V$ model but is solely based upon using the actual cell performance data and enables accurate prediction of programming time, given supply current ($I_{\text{S}}$). The full utilization of available supply current renders the programming speed much faster and also enables reliable multi-bit soft-programming. The ramped gate scheme induces a strong self-convergence of the simultaneously up-shifted threshold voltages regardless of their initial values or the variations of the shift speed from cell to cell.
- Japan Society of Applied Physicsの論文
- 2005-04-10
著者
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KIM Bomsoo
Korea Institute for Advanced Study
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Min Hong
School Of Electrical Engineering & Isrc Seoul National University
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BAEK Chang-Ki
School of Electrical Engineering and Computer Science and Nano-Systems Institute (NSI-NCRC), Seoul N
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KWON Wookhyun
Korea Institute for Advanced Study
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Quan Wu-yun
Institute Of Microelectronics Fudan University
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Park Young
School Of Electrical And Computer Engineering Sungkyunkwan University
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Quan Wu-yun
Institute of Microelectronics, Fudan University, 220 Handan Road, Shanghai 200433, China
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Baek Chang-Ki
School of Electrical Engineering and Computer Science and Nano-Systems Institute (NSI-NCRC), Seoul National University, Seoul 151-744, Korea
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Min Hong
School of Electrical Engineering and Computer Science and Nano-Systems Institute (NSI-NCRC), Seoul National University, Seoul 151-744, Korea
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Kwon Wookhyun
Korea Institute for Advanced Study, 207-43 Cheongryangri, Seoul, Korea
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