A Compact Memory-Merged Vector-Matching Circuitry for Neuron-MOS Associative Processor (Special Issue on Integrated Electronics and New System Paradigms)
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概要
- 論文の詳細を見る
A new vector-matching circuit technology has been developed aiming at compact implementation of maximum likelihood search engine for neuron-MOS associative processor. The new matching cell developed in this work possessed the template information in the form of an analog mask ROM and calcufates the absolute value of difference between the template vector and the input vector components. The analog-mask ROM merged matching cell is composed of only five transistors to be compared with our earlier-version memory separated matching cell of 13 transistors. In addition, the undesirable cell-to-cell data interference through the common floating node ("boot-strap effect") has been eliminated without using power-consuming current source loads in source followers. As a result, dc-current-free matching cell operation has been established, making it possible to build a low-power, high-density search engine. Test circuits were fabricated by a 0.8-μm double-polysilicon double-metal nwell CMOS process, and the circuit operation has been experimentally verified.
- 社団法人電子情報通信学会の論文
- 1999-09-25
著者
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SHIBATA Tadashi
Department of Physics,Faculty of Science,Osaka University
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Shibata Tadashi
Department Of Information And Communication Engineering The University Of Tokyo
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Shibata T
Univ. Tokyo Tokyo Jpn
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Shibata T
Department Of Information And Communication Engineering The University Of Tokyo
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Ohmi Tadahiro
The New Industry Creation Hatchery Center (niche) Tohoku University
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Shibata Tadashi
Department Of Electrical Engineering And Information Systems School Of Engineering The University Of
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KONDA Masahiro
Graduate School of Engineering ,Department of Electronic Engineering, Tohoku University
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Konda Masahiro
Graduate School Of Engineering Department Of Electronic Engineering Tohoku University
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Shibata T
Ntt Photonics Laboratories Ntt Corporation:(present Address)ntt Science And Core Technology Group Nt
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Shibata Tadashi
Department of Electrical Engineering and Information System, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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