Superior Generalization Capability of Hardware-Learing Algorithm Developed for Self-Learning Neuron-MOS Neural Networks
スポンサーリンク
概要
- 論文の詳細を見る
We have investigated the learning performance of the hardware backpropagation (HBP) algorithm, a hardware-oriented learning algorithm developed for the self-learning architecture of neural networks constructed using neuron MOS (metal-oxide-semiconductor) transistors. The solution to finding a mirror symmetry axis in a 4×4 binary pixel array was tested by computer simulation based on the HBP algorithm. Despite the inherent restrictions imposed on the hardware-learning algorithm, HBP exhibits equivalent learning performance to that of the original backpropagation (BP) algorithm when all the pertinent parameters are optimized. Very importantly, we have found that HBP has a superior generalization capability over BP; namely, HBP exhibits higher performance insolving problems that the network has not yet learnt.
- 社団法人応用物理学会の論文
- 1995-02-28
著者
-
Shibata Tadashi
Department Of Electrical Engineering And Information Systems School Of Engineering The University Of
-
Ohmi Tadahiro
Department Of Electronic Engineering
-
Kondo Shuhei
Department of Electronic Engineering
-
Shibata Tadashi
Department Of Electronic Engineering
-
Kondo S
Kansai Electric Power Inc. Jpn
-
Shibata Tadashi
Department of Electrical Engineering and Information System, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
関連論文
- Electron Spin Resonance in One-Dimensional Antiferromagnet CuGeO_3
- Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects
- Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology (Special Issue on Integrated Electronics and New System Paradigms)
- Minimization of BF^+_2-Implantation Dose to Reduce the Annealing Time for Ultra-Shallow Source/Drain Junction Formation below 600℃
- Reduction of BF2+-Implantation Dose to Minimize the Annealing Time for Ultra-Shallow Source/Drain Junction Formation below 600℃
- A Comparative Examination of Ion Implanted n^+p Junctions Annealed at 1000℃ and 450℃
- Formation of Ultra-Shallow and Low-Leakage p^+n Junctions by Low-Temperature Post-Implantation Annealing
- Effect of Substrate Boron Concentration on the Integrity of 450℃-Annealed Ion-Implanted Junctions
- Reducing Reverse-Bias Current in 450℃-Annealed n^+p Junction by Hydrogern Radical Sintering
- Neuron MOS Analog/Digital Merged Circuit Technology For Center-Of-Mass Tracker Circuit
- Oscillatory High-Field Magnetization in LaP Doped with Ce
- An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations
- Ultra-Low-Temperature Formation of Si Nitride Film by Direct Nitridation Employing High-Density and Low-Energy Ion Bombardment
- Silicon Wafer Orientation Dependence of Metal Oxide Sermiconductor Device Reliability
- Ultra Low-Temperature Growth of High-Integrity Thin Gate Oxide Films by Low-Energy Ion-Assisted Oxidation
- Preoxide-Controlled Oxidation for Very Thin Oxide Films
- Native Oxide Growth on Silicon Surface in Ultrapure Water and Hydrogen Peroxide
- Dopant-Free Channel Transistor with Punchthrough Control Region under Source and Drain
- Formation of Ultra-Shallow and Low-Reverse-Bias-Current Tantalum-Silicided Junctions Using a Si-Eneapsulated Silicidation Technique and Low-Temperature Furnace Annealing below 550℃
- Formation of Ultra-Shallow, Low-Leakage and Low-Contact-Resistance Junctions by Low-Temperature Si-Encapsulated Silicidation Process
- A Compact Memory-Merged Vector-Matching Circuitry for Neuron-MOS Associative Processor (Special Issue on Integrated Electronics and New System Paradigms)
- Design of Radial Line Slot Antennas at 8.3 GHz for Large Area Uniform Plasma Generation
- Abrupt and Arbitrary Profile Formation in Silicon Using a Low-Kinetic-Energy Ion Bombardment Process
- Impact of High-Precision RF-Plasma Control on Very-Low-Temperature Silicon Epitaxy
- Improvement of Rinsing Efficiency after Sulfuric Acid Hydrogen Peroxide Mixture (H_2SO_4/H_2O_2) by HF Addition
- Characterization and Control of Native Oxide on Silicon
- Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Model for the Electrochemical Deposition and Removal of Metallic Impurities on Si Surfaces (Special Issue on Scientific ULSI Manufacturing Technology)
- Minimizing Wafer Surface Damage and Chamber Material Contamination in New Plasma Processing Equipment
- Planar-Type Gunn Diode of InP
- Development of Scanning μ-RHEED Microscopy for Imaging Polycrystal Grain Structure in LSI (SOLID STATE DEVICES AND MATERIALS 1)
- Very-Low-Temperature Epitaxial Silicon Growth By Low-Kinetic-Energy Particle Bombardment : Silicon Devices and Process Technologies(Solid State Devices and Materials 1)
- An Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects
- Hot-Carrier-Immunity Degradation in Metal Oxide Semiconductor Field Effect Transistors Caused by Ion-Bombardment Processes
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (画像工学)
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (信号処理)
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (集積回路)
- Effect of Preoxide on the Structure of Thernmal Oxide
- A Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible MIMD Elements
- A High-Performance Ramp-Voltage-Scan Winner-Take-All Circuit in an Open Loop Architecture
- A High-Performance Time-Domain Winner-Take-All Circuit Employing OR-Tree Architecture
- Native Oxide Growing Behavior on Si Crystal Structure and Resistivity
- Automatic Defect Pattern Detection on LSI Wafers Using Image Processing Techniques
- Optimizing Vector-Quantization Processor Architecture for Intelligent Query-Search Applications
- Optimizing Associative Processor Architecture for Intelligent Internet Search Applications
- The Nature of Metallic Contamination on Various Silicon Substrates
- In Situ Observation of Electromigration in Cu Film Using Scanning μ-Reflection High-Energy Electron Diffraction Microscope
- In Situ Chamber Cleaning Using Halogenated-Gas Plasmas Evaluated by Plasma-Parameter Extraction
- Modeling and Analysis of RF Plasma Using Electrical Equivalent Circuit
- A Compact and Power-Efficient Implementation of Rank Order Filters Using Time-Domain Digital Computation Technique
- Effect of Silicon Wafer In Situ Cleaning on the Chemical Structure of Ultrathin Silicon Oxide Film
- Formation Process of Highly Reliable Ultra-Thin Gate Oxide
- Dielectric Relaxation Effect of Traveling Carriers in the Semiconductors
- Gas Chemistry Dependence of Si Surface Reactions in a Fluorocarbon Plasma during Contact Hole Etching
- Dependence of Gas Chemistry on Si Surface Reactions in High C/F Ratio Fluorocarbon Plasma during Contact Hole Etching
- Trends for Future Silicon Technology
- Time-Dependent Dielectric Degradation (TDDD) Influenced by Ultrathin Oxidation Process
- Neuron-MOS Parallel Search Hardware for Real-Time Signal Processing
- High-Reliability Lithography Performed by Ultrasonic and Surfactant-Added Developing System
- High-Sensitivity and High-Resolution Contact Hole Patterning by Enhanced-Wettability Developer
- Metallic Impurity Growing Behavior on Surface Crystal Structure
- Study on an Angular Momentum Conservation of Radiation in a Uniaxial Crystal
- Static Negative Resistance in Highly Doped Gunn Diodes and Application to Switching and Amplification
- Superior Generalization Capability of Hardware-Learing Algorithm Developed for Self-Learning Neuron-MOS Neural Networks
- Intelligent Signal Processing Based on a Psychologically-Inspired VLSI Brain Model(Special Section on the Trend of Digital Signal Processing and Its Future Direction)
- Functionality Enhancement in Elemental Devices for Implementing Intelligence on Integrated Circuits (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Moving-Object-Localization Hardware Algorithm Employing OR-Amplification of Pixel Activities
- Specialty Gas Interactions with Various Silicon Surfaces
- A Compact Bell-Shaped Analog Matching Cell Module for Digital-Memory-Based Associative Processors
- Selective Tungsten Chemical Vapor Deposition with High Deposition Rate for ULSI Application
- Four-Terminal Device Electronics for Intelligent Silicon Integrated Systems
- An Edge Cache Memory Architecture for Early Visual Processing VLSIs
- FOREWORD (Special Section on Digital Signal Processing)
- Hardware Architecture for Pseudo-2D Hidden-Markov-Model-Based Face Recognition System Employing Laplace Distribution Functions
- Strategy in Cleaning Processes for Future Materials
- Compact Bell-Shaped Analog Matching-Cell Module for Digital-Memory-Based Associative Processors
- Contamination-Free Physical Resist Stripping by Megasonic/IPA/Fluoride Enhanced Life-off Processing
- Fully Parallel Self-Learning Analog Support Vector Machine Employing Compact Gaussian Generation Circuits (Special Issue : Solid State Devices and Materials (2))
- Efficient Image-Vector-Generation Processor for Edge-Based Complementary Feature Representations
- A Hardware-Implementation-Friendly Pulse-Coupled Neural Network Algorithm for Analog Image-Feature-Generation Circuits
- A Simple Random Noise Generator Employing Metal-Oxide-Semiconductor-Field-Effect-Transistor Channel $kT/C$ Noise and Low-Capacitance Loading Buffer
- Enhancement of Silicon Epitaxy by Increased Phosphorus Concentration in a Low-Energy Ion Bombardment Process
- Hardware Architecture for Pseudo-Two-Dimensional Hidden-Markov-Model-Based Face Recognition Systems Employing Laplace Distribution Functions
- Moving-Object-Localization Hardware Algorithm Employing OR-Amplification of Pixel Activities
- Real-Time Very Large-Scale Integration Recognition System with an On-Chip Adaptive K-Means Learning Algorithm
- Compact and Power-Efficient Implementation of Rank-Order Filters Using Time-Domain Digital Computation Technique
- Formation of Ultra-Shallow and Low-Reverse-Bias-Current Tantalum-Silicided Junctions Using a Si-Encapsulated Silicidation Technique and Low-Temperature Furnace Annealing below 550°C
- Improvement of Rinsing Efficiency after Sulfuric Acid Hydrogen Peroxide Mixture ( H2SO4/H2O2) by HF Addition
- A Digital-Pixel-Sensor-Based Global Feature Extraction Processor for Real-Time Object Recognition
- Time-Dependent Dielectric Degradation (TDDD) Influenced by Ultrathin Film Oxidation Process
- Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible Multiple-Instruction-Stream Multiple-Data-Stream Elements
- A Binary-Tree Hierarchical Multiple-Chip Architecture for Real-Time Large-Scale Learning Processor Systems