Optimizing Vector-Quantization Processor Architecture for Intelligent Query-Search Applications
スポンサーリンク
概要
- 論文の詳細を見る
- 社団法人応用物理学会の論文
- 2002-04-30
著者
-
SHIBATA Tadashi
Department of Physics,Faculty of Science,Osaka University
-
MITA Yoshio
Department of Electrical Engineering, School of Engineering, The University of Tokyo
-
三田 吉郎
東大
-
Shibata Tadashi
Department Of Electrical Engineering And Information Systems School Of Engineering The University Of
-
XU Huaiyu
Department of Electronic Engineering, The University of Tokyo
-
Xu Huaiyu
Department Of Electronic Engineering The University Of Tokyo
-
SHIBATA Tadashi
Department of Frontier Informatics, The University of Tokyo
-
MITA Yoshio
Department of Electronic Engineering, The University of Tokyo
-
Shibata Tadashi
Department of Electrical Engineering and Information System, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
関連論文
- Electron Spin Resonance in One-Dimensional Antiferromagnet CuGeO_3
- 理科系の国フランス : INRIA滞在記(グローバル・アイ)
- ナノ開口・大開口のエッチングを可能とする輪郭描画法
- Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects
- An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations
- Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology (Special Issue on Integrated Electronics and New System Paradigms)
- A Comparative Examination of Ion Implanted n^+p Junctions Annealed at 1000℃ and 450℃
- Effect of Substrate Boron Concentration on the Integrity of 450℃-Annealed Ion-Implanted Junctions
- Reducing Reverse-Bias Current in 450℃-Annealed n^+p Junction by Hydrogern Radical Sintering
- Neuron MOS Analog/Digital Merged Circuit Technology For Center-Of-Mass Tracker Circuit
- Oscillatory High-Field Magnetization in LaP Doped with Ce
- An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations
- (マイクロマシン特集号)
- マイクロマシンによるファブリペロー型波長可変フィルタの作製と光ファイバへの結合
- 電気的、機械的、光学的デバイスのアセンブリを目指したマイクロコネクタの製作と評価
- 2P1-3F-D4 多数マイクロマシンを用いた物体搬送システムの制御手法に関する研究 : 自律分散搬送システムを指向した MEMS
- 2A1-A09 バルクマイクロマシニングによるアレイ型エアーフローアクチェータ : 自律分散搬送システムを指向した MEMS
- (マイクロマシン特集号)
- 遅延マスク法によるシリコンの3次元バルクマイクロ構造
- マイクロマシンとの集積化に適したフィードバック制御用分散型プロセッサ(マイクロマシン関連技術)
- 形状認識を行なう分散型マイクロ搬送システム
- マイクロ搬送システムに適した分散的頂点検出による物体識別
- シリコン基板の異方性エッチングによるマイクロコネクタ (マイクロマシン)
- 自律分散型マイクロ搬送システムの実現
- 自律分散型搬送システムの制御系の考案と実現
- A Compact Memory-Merged Vector-Matching Circuitry for Neuron-MOS Associative Processor (Special Issue on Integrated Electronics and New System Paradigms)
- Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis (Special Issue on New Concept Device and Novel Architecture LSIs)
- Minimizing Wafer Surface Damage and Chamber Material Contamination in New Plasma Processing Equipment
- An Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects
- Hot-Carrier-Immunity Degradation in Metal Oxide Semiconductor Field Effect Transistors Caused by Ion-Bombardment Processes
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (画像工学)
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (信号処理)
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (集積回路)
- Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible Multiple-Instruction-Stream Multiple-Data-Stream Elements
- A Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible MIMD Elements
- A High-Performance Ramp-Voltage-Scan Winner-Take-All Circuit in an Open Loop Architecture
- A High-Performance Time-Domain Winner-Take-All Circuit Employing OR-Tree Architecture
- Automatic Defect Pattern Detection on LSI Wafers Using Image Processing Techniques
- Optimizing Vector-Quantization Processor Architecture for Intelligent Query-Search Applications
- Optimizing Associative Processor Architecture for Intelligent Internet Search Applications
- A Compact and Power-Efficient Implementation of Rank Order Filters Using Time-Domain Digital Computation Technique
- Neuron-MOS Parallel Search Hardware for Real-Time Signal Processing
- Result of combined treatment with transcatheter hapatic arterial chemoembolization and whole-liver irradiation with the moving strip technique in unresectable hepatocellular carcinoma
- Superior Generalization Capability of Hardware-Learing Algorithm Developed for Self-Learning Neuron-MOS Neural Networks
- Intelligent Signal Processing Based on a Psychologically-Inspired VLSI Brain Model(Special Section on the Trend of Digital Signal Processing and Its Future Direction)
- Functionality Enhancement in Elemental Devices for Implementing Intelligence on Integrated Circuits (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Moving-Object-Localization Hardware Algorithm Employing OR-Amplification of Pixel Activities
- A Compact Bell-Shaped Analog Matching Cell Module for Digital-Memory-Based Associative Processors
- Four-Terminal Device Electronics for Intelligent Silicon Integrated Systems
- An Edge Cache Memory Architecture for Early Visual Processing VLSIs
- FOREWORD (Special Section on Digital Signal Processing)
- Hardware Architecture for Pseudo-2D Hidden-Markov-Model-Based Face Recognition System Employing Laplace Distribution Functions
- Compact Bell-Shaped Analog Matching-Cell Module for Digital-Memory-Based Associative Processors
- Fully Parallel Self-Learning Analog Support Vector Machine Employing Compact Gaussian Generation Circuits (Special Issue : Solid State Devices and Materials (2))
- Efficient Image-Vector-Generation Processor for Edge-Based Complementary Feature Representations
- A Hardware-Implementation-Friendly Pulse-Coupled Neural Network Algorithm for Analog Image-Feature-Generation Circuits
- A Simple Random Noise Generator Employing Metal-Oxide-Semiconductor-Field-Effect-Transistor Channel $kT/C$ Noise and Low-Capacitance Loading Buffer
- Hardware Architecture for Pseudo-Two-Dimensional Hidden-Markov-Model-Based Face Recognition Systems Employing Laplace Distribution Functions
- Moving-Object-Localization Hardware Algorithm Employing OR-Amplification of Pixel Activities
- Real-Time Very Large-Scale Integration Recognition System with an On-Chip Adaptive K-Means Learning Algorithm
- Compact and Power-Efficient Implementation of Rank-Order Filters Using Time-Domain Digital Computation Technique
- A Digital-Pixel-Sensor-Based Global Feature Extraction Processor for Real-Time Object Recognition
- Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible Multiple-Instruction-Stream Multiple-Data-Stream Elements
- A Binary-Tree Hierarchical Multiple-Chip Architecture for Real-Time Large-Scale Learning Processor Systems
- Micro-Fluidic Channel Integration on Thick-SOI LSI Device for Biological Application.