An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations
スポンサーリンク
概要
- 論文の詳細を見る
In this paper, a motion field representation algorithm based on directional edge information has been developed. This work is aiming at building an ego-motion detection system using dedicated VLSI chips developed for real time motion field generation at low powers[1],[2]. Directional edge maps are utilized instead of original gray-scale images to represent local features of an image and to detect the local motion component in a moving image sequence. Motion detection by edge histogram matching has drastically reduced the computational cost of block matching, while achieving a robust performance of the ego-motion detection system under dynamic illumination variation. Two kinds of feature vectors, the global motion vector and the component distribution vectors, are generated from a motion field at two different scales and perspectives. They are jointly utilized in the hierarchical classification scheme employing multiple-clue matching. As a result, the problems of motion ambiguity as well as motion field distortion caused by camera shaking during video capture have been resolved. The performance of the ego-motion detection system was evaluated under various circumstances, and the effectiveness of this work has been verified.
著者
-
SHIBATA Tadashi
Department of Physics,Faculty of Science,Osaka University
-
HAO Jia
Department of Electrical Engineering and Information Systems, The University of Tokyo
関連論文
- Electron Spin Resonance in One-Dimensional Antiferromagnet CuGeO_3
- Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects
- An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations
- Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology (Special Issue on Integrated Electronics and New System Paradigms)
- A Comparative Examination of Ion Implanted n^+p Junctions Annealed at 1000℃ and 450℃
- Effect of Substrate Boron Concentration on the Integrity of 450℃-Annealed Ion-Implanted Junctions
- Reducing Reverse-Bias Current in 450℃-Annealed n^+p Junction by Hydrogern Radical Sintering
- Neuron MOS Analog/Digital Merged Circuit Technology For Center-Of-Mass Tracker Circuit
- Oscillatory High-Field Magnetization in LaP Doped with Ce
- An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations
- Quercetin Prevents Cardiac Hypertrophy Induced by Pressure Overload in Rats
- A Compact Memory-Merged Vector-Matching Circuitry for Neuron-MOS Associative Processor (Special Issue on Integrated Electronics and New System Paradigms)
- Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis (Special Issue on New Concept Device and Novel Architecture LSIs)
- Minimizing Wafer Surface Damage and Chamber Material Contamination in New Plasma Processing Equipment
- An Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects
- Hot-Carrier-Immunity Degradation in Metal Oxide Semiconductor Field Effect Transistors Caused by Ion-Bombardment Processes
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (画像工学)
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (信号処理)
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (集積回路)
- Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible Multiple-Instruction-Stream Multiple-Data-Stream Elements
- A Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible MIMD Elements
- A High-Performance Ramp-Voltage-Scan Winner-Take-All Circuit in an Open Loop Architecture
- A High-Performance Time-Domain Winner-Take-All Circuit Employing OR-Tree Architecture
- Automatic Defect Pattern Detection on LSI Wafers Using Image Processing Techniques
- Optimizing Vector-Quantization Processor Architecture for Intelligent Query-Search Applications
- Optimizing Associative Processor Architecture for Intelligent Internet Search Applications
- A Compact and Power-Efficient Implementation of Rank Order Filters Using Time-Domain Digital Computation Technique
- Neuron-MOS Parallel Search Hardware for Real-Time Signal Processing