Moving-Object-Localization Hardware Algorithm Employing OR-Amplification of Pixel Activities
スポンサーリンク
概要
- 論文の詳細を見る
A hardware algorithm for real-time moving-object localization has been developed using pixel activities as the primary clue. The temporal differences in pixel intensities are calculated from two consecutive-frame images to produce a pixel activity map, which is then binarized using the threshold adaptively determined. The activity bits thus produced are projected onto $x$- and $y$-axes, and activity histograms are generated for use in localizing moving objects. The most difficult issue in such an approach is how to determine the threshold that is used to generate the activity bits. The concept of "OR-amplification" has been developed, in which the activity bits due to moving objects and those due to other origins are differentiated by dynamically observing the change in their appearance as the threshold value is dynamically varied. The proposed hardware algorithm has been verified by computer simulation. A proof-of-concept test chip was designed on the basis of 0.18 μm complementary metal–oxide–semiconductor (CMOS) technology, and the proper operation of the circuit was demonstrated by circuit simulation.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2008-04-25
著者
-
Shibata Tadashi
Department Of Electrical Engineering And Information Systems School Of Engineering The University Of
-
Niki Yusuke
Department Of Frontier Informatics School Of Frontier Sciences The University Of Tokyo
-
Manzawa Yasuo
Department Of Frontier Informatics School Of Frontier Sciences The University Of Tokyo
-
Kametani Satoshi
Department Of Frontier Informatics School Of Frontier Sciences The University Of Tokyo
-
Kametani Satoshi
Department of Frontier Informatics, Graduate School of Frontier Sciences, The University of Tokyo, 5-1-5 Kashiwanoha, Kashiwa, Chiba 277-8561, Japan
-
Manzawa Yasuo
Department of Frontier Informatics, Graduate School of Frontier Sciences, The University of Tokyo, 5-1-5 Kashiwanoha, Kashiwa, Chiba 277-8561, Japan
-
Niki Yusuke
Department of Frontier Informatics, Graduate School of Frontier Sciences, The University of Tokyo, 5-1-5 Kashiwanoha, Kashiwa, Chiba 277-8561, Japan
-
Shibata Tadashi
Department of Electrical Engineering and Information System, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
関連論文
- Electron Spin Resonance in One-Dimensional Antiferromagnet CuGeO_3
- Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects
- Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology (Special Issue on Integrated Electronics and New System Paradigms)
- A Comparative Examination of Ion Implanted n^+p Junctions Annealed at 1000℃ and 450℃
- Effect of Substrate Boron Concentration on the Integrity of 450℃-Annealed Ion-Implanted Junctions
- Reducing Reverse-Bias Current in 450℃-Annealed n^+p Junction by Hydrogern Radical Sintering
- Neuron MOS Analog/Digital Merged Circuit Technology For Center-Of-Mass Tracker Circuit
- Oscillatory High-Field Magnetization in LaP Doped with Ce
- An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations
- A Compact Memory-Merged Vector-Matching Circuitry for Neuron-MOS Associative Processor (Special Issue on Integrated Electronics and New System Paradigms)
- Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis (Special Issue on New Concept Device and Novel Architecture LSIs)
- Minimizing Wafer Surface Damage and Chamber Material Contamination in New Plasma Processing Equipment
- An Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects
- Hot-Carrier-Immunity Degradation in Metal Oxide Semiconductor Field Effect Transistors Caused by Ion-Bombardment Processes
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (画像工学)
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (信号処理)
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (集積回路)
- A Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible MIMD Elements
- A High-Performance Ramp-Voltage-Scan Winner-Take-All Circuit in an Open Loop Architecture
- A High-Performance Time-Domain Winner-Take-All Circuit Employing OR-Tree Architecture
- Automatic Defect Pattern Detection on LSI Wafers Using Image Processing Techniques
- Optimizing Vector-Quantization Processor Architecture for Intelligent Query-Search Applications
- Optimizing Associative Processor Architecture for Intelligent Internet Search Applications
- A Compact and Power-Efficient Implementation of Rank Order Filters Using Time-Domain Digital Computation Technique
- Neuron-MOS Parallel Search Hardware for Real-Time Signal Processing
- Superior Generalization Capability of Hardware-Learing Algorithm Developed for Self-Learning Neuron-MOS Neural Networks
- Intelligent Signal Processing Based on a Psychologically-Inspired VLSI Brain Model(Special Section on the Trend of Digital Signal Processing and Its Future Direction)
- Functionality Enhancement in Elemental Devices for Implementing Intelligence on Integrated Circuits (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Moving-Object-Localization Hardware Algorithm Employing OR-Amplification of Pixel Activities
- A Compact Bell-Shaped Analog Matching Cell Module for Digital-Memory-Based Associative Processors
- Four-Terminal Device Electronics for Intelligent Silicon Integrated Systems
- An Edge Cache Memory Architecture for Early Visual Processing VLSIs
- FOREWORD (Special Section on Digital Signal Processing)
- Hardware Architecture for Pseudo-2D Hidden-Markov-Model-Based Face Recognition System Employing Laplace Distribution Functions
- Compact Bell-Shaped Analog Matching-Cell Module for Digital-Memory-Based Associative Processors
- Fully Parallel Self-Learning Analog Support Vector Machine Employing Compact Gaussian Generation Circuits (Special Issue : Solid State Devices and Materials (2))
- Efficient Image-Vector-Generation Processor for Edge-Based Complementary Feature Representations
- A Hardware-Implementation-Friendly Pulse-Coupled Neural Network Algorithm for Analog Image-Feature-Generation Circuits
- A Simple Random Noise Generator Employing Metal-Oxide-Semiconductor-Field-Effect-Transistor Channel $kT/C$ Noise and Low-Capacitance Loading Buffer
- Hardware Architecture for Pseudo-Two-Dimensional Hidden-Markov-Model-Based Face Recognition Systems Employing Laplace Distribution Functions
- Moving-Object-Localization Hardware Algorithm Employing OR-Amplification of Pixel Activities
- Real-Time Very Large-Scale Integration Recognition System with an On-Chip Adaptive K-Means Learning Algorithm
- Compact and Power-Efficient Implementation of Rank-Order Filters Using Time-Domain Digital Computation Technique
- A Digital-Pixel-Sensor-Based Global Feature Extraction Processor for Real-Time Object Recognition
- Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible Multiple-Instruction-Stream Multiple-Data-Stream Elements
- A Binary-Tree Hierarchical Multiple-Chip Architecture for Real-Time Large-Scale Learning Processor Systems