Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis (Special Issue on New Concept Device and Novel Architecture LSIs)

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概要

• 論文の詳細を見る

• The problem of large power dissipation in the conventional Neuron MOS (υM0S) inverter has been resolved by introducing a newly developed deep threshold υMOS inverter. This deep threshold υMOS inverter has a very simple circuit configuration composed of a υM0S inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new υMOS inverter has been reduced by a factor of 1/30 as compared to conventional υMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new υMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.

• 1997-07-25

著者

• SHIBATA Tadashi

  Department of Physics,Faculty of Science,Osaka University

• Kotani K

  Department Of Electronic Engineering Graduate School Of Engineering Tohoku University

• Kotani Koji

  Graduate School Of Engineering Tohoku University

• Shibata Tadashi

  Department Of Information And Communication Engineering The University Of Tokyo

• Shibata T

  Univ. Tokyo Tokyo Jpn

• Shibata T

  Department Of Information And Communication Engineering The University Of Tokyo

• Kotani Koji

  Laboratory For Electronic Intelligent Systems Research Institute Of Electrical Communication Tohoku

• Ohmi Tadahiro

  Department Of Electronic Engineering Graduate School Of Engineering Tohoku University

• Shibata Tadashi

  Department Of Electrical Engineering And Information Systems School Of Engineering The University Of

• Kotani K

  Tohoku Univ. Sendai‐shi Jpn

• Ohmi Tadahiro

  Department Of Electronic Engineering

• Shibata T

  Ntt Photonics Laboratories Ntt Corporation:(present Address)ntt Science And Core Technology Group Nt

• KWON Ho-Yup

  Department of Electronic Engineering, Tohoku University

• Shibata Tadashi

  Department of Electrical Engineering and Information System, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan

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