Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology (Special Issue on Integrated Electronics and New System Paradigms)
スポンサーリンク
概要
- 論文の詳細を見る
An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fullyparallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-μm double-polysilicon CMOS technology with the chip size of 7.2 mm × 7.2 mm, and the basic operation of the circuits has been demonstrated.
- 社団法人電子情報通信学会の論文
- 1999-09-25
著者
-
SHIBATA Tadashi
Department of Physics,Faculty of Science,Osaka University
-
Shibata Tadashi
Department Of Information And Communication Engineering The University Of Tokyo
-
Nakada A
Vlsi Design And Education Center The University Of Tokyo
-
OHMI Tadahiro
New Industry Creation Hatchery Center, Tohoku University
-
Shibata T
Univ. Tokyo Tokyo Jpn
-
Shibata T
Department Of Information And Communication Engineering The University Of Tokyo
-
NAKADA Akira
VLSI Design and Education Center, The University of Tokyo
-
KONDA Masahiro
Department of Electronic Engineering, Graduate School of Engineering, Tohoku University
-
MORIMOTO Tatsuo
Department of Electronic Engineering, Graduate School of Engineering, Tohoku University
-
YONEZAWA Takemi
Department of Electronic Engineering, Graduate School of Engineering, Tohoku University
-
Shibata Tadashi
Department Of Electrical Engineering And Information Systems School Of Engineering The University Of
-
KONDA Masahiro
Graduate School of Engineering ,Department of Electronic Engineering, Tohoku University
-
Ohmi Tadahiro
New Industry Creation Hatchery Center Future Information Industry Creation Center Tohoku University
-
Konda Masahiro
Graduate School Of Engineering Department Of Electronic Engineering Tohoku University
-
Shibata T
Ntt Photonics Laboratories Ntt Corporation:(present Address)ntt Science And Core Technology Group Nt
-
Nakada Akira
Vlsi Design And Education Center The University Of Tokyo
-
Morimoto T
Nec Corp. Otsu‐shi Jpn
-
Yonezawa Takemi
Department Of Electronic Engineering Graduate School Of Engineering Tohoku University
-
Ohmi Tadahiro
New Industry Creation Hatchery Center (niche) Tohoku University
-
Shibata Tadashi
Department of Electrical Engineering and Information System, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
関連論文
- High current drivability FD-SOI CMOS with low Source/Drain series resistance (Silicon devices and materials)
- Electron Spin Resonance in One-Dimensional Antiferromagnet CuGeO_3
- Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects
- An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations
- High Current Drivability FD-SOI CMOS with Low Source/Drain Series Resistance(Session 9B : Nano-Scale devices and Physics)
- High Current Drivability FD-SOI CMOS with Low Source/Drain Series Resistance(Session 9B : Nano-Scale devices and Physics)
- Subvector-Based Fast Encoding Method for Vector Quantization Without Using Two Partial Variances
- Performance Comparison between Equal-Average Equal-Variance Equal-Norm Nearest Neighbor Search (EEENNS) Method and Improved Equal-Average Equal-Variance Nearest Neighbor Search (IEENNS) Method for Fast Encoding of Vector Quantization(Image Processing and
- Fast Encoding Method for Image Vector Quantization Based on Multiple Appropriate Features to Estimate Euclidean Distance
- A Fast Encoding Method for Vector Quantization Using Modified Memory-Efficient Sum Pyramid
- A Fast Search Method for Vector Quantization Using Enhanced Sum Pyramid Data Structure(Image)
- An Improved Fast Encoding Algorithm for Vector Quantization Using 2-Pixel-Merging Sum Pyramid and Manhattan-Distance-First Check(Image Processing, Image Pattern Recognition)
- A Fast Encoding Method for Vector Quantization Using L_1 and L_2 Norms to Narrow Necessary Search Scope(Image Processing, Image Pattern Recognition)
- A Fast Encoding Method for Vector Quantization Based on 2-Pixel-Merging Sum Pyramid Data Structure(Image)
- A nonlinear cepstral compensation method for noisy speech processing (音声言語情報処理 研究報告 第1回音声言語シンポジウム(SPLC))
- Extracting person's speech individually from original records of meeting by speaker identification technique
- Control of nitrogen profile in radical nitridation of SiO_2 films
- Tribological study for low shear force CMP process on damascene interconnects (シリコン材料・デバイス)
- Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology (Special Issue on Integrated Electronics and New System Paradigms)
- Minimization of BF^+_2-Implantation Dose to Reduce the Annealing Time for Ultra-Shallow Source/Drain Junction Formation below 600℃
- Reduction of BF2+-Implantation Dose to Minimize the Annealing Time for Ultra-Shallow Source/Drain Junction Formation below 600℃
- A Comparative Examination of Ion Implanted n^+p Junctions Annealed at 1000℃ and 450℃
- Formation of Ultra-Shallow and Low-Leakage p^+n Junctions by Low-Temperature Post-Implantation Annealing
- Effect of Substrate Boron Concentration on the Integrity of 450℃-Annealed Ion-Implanted Junctions
- Reducing Reverse-Bias Current in 450℃-Annealed n^+p Junction by Hydrogern Radical Sintering
- Impact of fully depleted silicon-on-insulator accumulation-mode CMOS on Si(110) (シリコン材料・デバイス)
- Neuron MOS Analog/Digital Merged Circuit Technology For Center-Of-Mass Tracker Circuit
- Oscillatory High-Field Magnetization in LaP Doped with Ce
- Performance Comparison of Ultra-thin FD-SOI Inversion-, Intrinsic- and Accumulation-Mode MOSFETs
- An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations
- Highly Reliable MOS Trench Gate FET by Oxygen Radical Oxidation
- Improved J-E Characteristics and Stress Induced Leakage Currents (SILC) in Oxynitride Films Grown at 400℃ by Microwave-Excited High-Density Kr/O_2/NH_3 Plasma
- Low Temperature Gate Oxidation MOS Transistor Produced by Kr/O_2 Microwave Excited High-Density Plasma
- Ultra-Thin Silicon Oxynitride Film Grown at Low-Temperature by Microwave-Excited High-Density Kr/O_2/N_2 Plasma
- Ultra-Thin Silicon Oxynitride Films as Cu Diffusion Barrier for Lowering Interconnect Resistivity
- High-Integrity Silicon Oxide Grown at Low-Temperature by Atomic Oxygen Generated in High-Density Krypton Plasma
- Low-Temperature Formation of Silicon Nitride Film by Direct Nitridation Employing High-Density and Low-Energy Ion Bombardment
- Effect of in-situ Formed Interlayer at Ta-SiO_2 interface on Performance and Reliability in Ta-Gate MOS Devices
- A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation(Optical)
- A Fine-Grained Programmable Logic Module with Small Amount of Configuration Data for Dynamically Reconfigurable Field-Programmable Gate Array
- Study on Compositional Transition Layers at Gate Dielectrics/Si Interface by using Angle-resolved X-ray Photoelectron Spectroscopy
- Study on Compositional Transition Layers at Gate Dielectrics/Si Interface by using Angle-resolved X-ray Photoelectron Spectroscopy
- A Technology for Reducing Flicker Noise for ULSI Applications
- High-Quality Silicon Oxide Film Formed by Diffusion Region Plasma Enhanced Chemical Vapor Deposition and Oxygen Radical Treatment Using Microwave-Excited High-Density Plasma
- Direct Optical Injection Locking of a 100-GHz-Class Oscillator IC Using a Back-Illuminated InP/InGaAs HPT and Its Applications(MWP Devices)(Special Issue on Recent Progress in Microwave and Millimeter-wave Photonics Technologies)
- Thin and Low-Resistivity Tantalum Nitride Diffusion Barrier and Giant-Grain Copper Interconnects for Advanced ULSI Metallization
- Thin and Low-Resistivity Tantalum Nitride Diffusion Barrier and Giant-Grain Copper Interconnects for Advanced ULSI Metallization
- Dopant-Free Channel Transistor with Punchthrough Control Region under Source and Drain
- Nitrogen Profile Study for SiON Gate Dielectrics of Advanced DRAM
- A Compact Memory-Merged Vector-Matching Circuitry for Neuron-MOS Associative Processor (Special Issue on Integrated Electronics and New System Paradigms)
- Characterizing Film Quality and Electromigration Resistance of Giant-Grain Copper Interconnects (Special Issue on Sub-Half Micron Si Device and Process Technologies)
- Data Analysis Technique of Atomic Force Microscopy for Atomically Flat Silicon Surfaces
- Low Contact Resistance with Low Schottky Barrier for N-type Silicon Using Yttrium Silicide
- Very Low Bit Error Rate in Flash Memory using Tunnel Dielectrics formed by Kr/O_2/NO Plasma Oxynitridation
- PVD Tantalum Oxide with Buffer Silicon Nitride Stacked High-k MIS Structure Using Low Temperature and High Density Plasma Processing
- Improved Transconductance and Gate Insulator Integrity of MISFETs with Si_3N_4 Gate Dielectric Fabricated by Microwave-Excited High-Density Plasma at 400℃
- Low Resistivity PVD TaNx/Ta/TaNx Stacked Metal Gate CMOS Technology Using Self-Grown bcc-Phased Tantalum on TaNx Buffer Layer
- A Statistical Analysis of Distributions of RTS Characteristics by Wide-Range Sampling Frequencies
- A Statistical Analysis of Distributions of RTS Characteristics by Wide-Range Sampling Frequencies
- A Material of Semiconductor Package with Low Dielectric Constant, Low Dielectric Loss and Flat Surface for High Frequency and Low Power Propagation(Session2: Silicon Devices I)
- A Material of Semiconductor Package with Low Dielectric Constant, Low Dielectric Loss and Flat Surface for High Frequency and Low Power Propagation(Session2: Silicon Devices I)
- The Evaluation of New Amorphous Hydrocarbon Film aCHx, for Copper Barrier Dielectric Film in Low-k Copper Metallization
- Low Dielectric Constant Non-Porous Fluorocarbon Films for Inter-Layer Dielectric
- Over-100-Gbit/s Multiplexing Operation of InP DHBT Selector IC Designed with High Collector-Current Density
- A High S/N Ratio Object Extraction CMOS Image Sensor with Column Parallel Signal Processing
- A Large-Signal MOSFET Model Based on Transient Carrier Response for RF Circuits
- A High S/N Ratio Object Extraction CMOS Image Sensor with Column Parallel Signal Processing
- Analysis of High-Speed Signal Behavior in a Miniaturized Interconnect(Special Issue on Advanced Sub-0.1μm CMOS Devices)
- Interconnect and Substrate Structure for Gigascale Integration
- Interconnect and Substrate Structure for High Speed Giga-Scale Integration
- Characterization of Zinc Oxide Films Grown by a Newly Developed Plasma Enhanced MOCVD Employing Microwave Excited High Density Plasma
- Damage-Free Microwave-Excited Plasma Contact Hole Etching without Carrier Deactivation at the Interface between Silicide and Heavily-Doped Si
- Influence of Interface Structure on Oxidation Rate of Silicon : Surfaces, Interfaces, and Films
- High-Speed Damage-Free Contact Hole Etching Using Dual Shower Head Microwave-Excited High-Density-Plasma Equipment
- Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Study on Reclaimed Photoresist Developer Using an Electrodialysis Method
- A Study on Reclaimed Photoresist Developer Using an Electrodialysis Method
- Ferroelectric Sr_2(Ta_, Nb_x)_2O_7 with a Low Dielectric Constant by Plasma Physical Vapor Deposition and Oxygen Radical Treatment
- Vertical Magnetoresistive / Inductive Head
- Minimizing Wafer Surface Damage and Chamber Material Contamination in New Plasma Processing Equipment
- An Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects
- Impact of High-Precision Processing on the Functional Enhancement of Neuron-MOS Integrated Circuits (Special Issue on Scientific ULSI Manufacturing Technology)
- Self-Aligned Aluminum-Gate MOSFET's Having Ultra-Shallow Junctions Formed by 450℃ Furnace Annealing (Special Issue on Sub-Half Micron Si Device and Process Technologies)
- Hot-Carrier-Immunity Degradation in Metal Oxide Semiconductor Field Effect Transistors Caused by Ion-Bombardment Processes
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (画像工学)
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (信号処理)
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (集積回路)
- Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible Multiple-Instruction-Stream Multiple-Data-Stream Elements
- A Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible MIMD Elements
- A High-Performance Ramp-Voltage-Scan Winner-Take-All Circuit in an Open Loop Architecture
- A High-Performance Time-Domain Winner-Take-All Circuit Employing OR-Tree Architecture
- Automatic Defect Pattern Detection on LSI Wafers Using Image Processing Techniques
- Optimizing Vector-Quantization Processor Architecture for Intelligent Query-Search Applications
- Optimizing Associative Processor Architecture for Intelligent Internet Search Applications
- W-band Waveguide Amplifier Module with InP-HEMT MMIC for Millimeter-wave Applications
- A Compact and Power-Efficient Implementation of Rank Order Filters Using Time-Domain Digital Computation Technique
- Experimental Results of Diversity Reception for Terrestrial Digital Broadcasting(Regular Section)
- A Novel Multi-Service Simultaneous Reception by Sharing Diversity Branches(Software Defined Radio Technology and Its Applications)
- OFDM Demodulation Method with Variable Effective Symbol Duration(Special Section on Multi-dimensional Mobile Information Networks)
- Neuron-MOS Parallel Search Hardware for Real-Time Signal Processing