New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (集積回路)
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概要
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A compact and power-efficient digital implementation of rank order filters compatible with focal-plane image processing has been developed based on a time-domain computation technique. The magnitude of an analog pixel intensity is represented as a pulse width in the pulse width modulation scheme and the rank order filtering is accomplished using simple digital adders and a binary counter. As a result, a very compact implementation comparable to analog counterparts has been achieved, while preserving the accuracy and programmability of digital implementation, this enable us to use the rank order filter as a building block in a parallel processing array. A test chip capable of performing multiple rank order filtering for up to 16 inputs was designed and fabricated in a 0.35-μm standard CMOS technology. Experimental results have demonstrated the correct operation of the circuit in a low power dissipation (0.44mW at 3.3V) with a very compact core size (0.014mm^2). The circuit has shown the speed performance of over 260K ranks/s at 8-bit resolution, which is more than sufficient for use at typical video frame rates. In addition, a new architecture for compact implementation of sorting engines with some modification in peripheral circuitries of the proposed rank order filtering architecture is also presented.
- 2007-10-18
著者
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SHIBATA Tadashi
Department of Physics,Faculty of Science,Osaka University
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Shibata Tadashi
Department Of Electrical Engineering And Information Systems School Of Engineering The University Of
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Nguyen Liem
Department Of Frontier Informatics School Of Frontier Sciences The University Of Tokyo
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ITO Kiyoto
Department of Frontier Informatics, School of Frontier Science, The University of Tokyo
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Shibata Tadashi
Department Of Frontier Informatics School Of Frontier Sciences The University Of Tokyo
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Ito Kiyoto
Department Of Frontier Informatics School Of Frontier Sciences The University Of Tokyo
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Shibata Tadashi
Department of Electrical Engineering and Information System, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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