A Simple Random Noise Generator Employing Metal-Oxide-Semiconductor-Field-Effect-Transistor Channel $kT/C$ Noise and Low-Capacitance Loading Buffer
スポンサーリンク
概要
- 論文の詳細を見る
An eight-transistor random noise generator employing a new circuit architecture has been developed. A compact two-transistor thermal noise source comprising a complementary metal-oxide-semiconductor (CMOS) inverter is proposed as a viable alternative to the area consuming conventional resistive noise source. The total extracted noise power is increased by reducing the effective capacitance at the output of the thermal noise source through the use of a unity-gain low-capacitance loading buffer. A wide-bandwidth high-noise-power random noise generator comprising the CMOS inverter noise source, a CMOS source follower as a low-capacitance loading buffer and a cascode amplifier as a high-gain stage, was fabricated and its noise generation capability experimentally verified. It has a very simple circuit configuration and is fully compatible with current VLSI technology, thus making it a promising candidate for integration of multiple random noise generators on a chip.
- Publication Office, Japanese Journal of Applied Physics, Faculty of Science, University of Tokyoの論文
- 2001-07-15
著者
-
Shibata Tadashi
Department Of Electrical Engineering And Information Systems School Of Engineering The University Of
-
Ohmi Tadahiro
New Industry Creation Hatchery Center (niche) Tohoku University
-
Ohmi Tadahiro
New Industry Creation Hatchery Center (NICHe), Tohoku University, Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan
-
Wee Keng
Department of Electronic Engineering, Tohoku University, Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan
-
Shibata Tadashi
Department of Frontier Informatics, School of Frontier Science, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan
-
Shibata Tadashi
Department of Electrical Engineering and Information System, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
関連論文
- Electron Spin Resonance in One-Dimensional Antiferromagnet CuGeO_3
- Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects
- High Current Drivability FD-SOI CMOS with Low Source/Drain Series Resistance(Session 9B : Nano-Scale devices and Physics)
- High Current Drivability FD-SOI CMOS with Low Source/Drain Series Resistance(Session 9B : Nano-Scale devices and Physics)
- Subvector-Based Fast Encoding Method for Vector Quantization Without Using Two Partial Variances
- Performance Comparison between Equal-Average Equal-Variance Equal-Norm Nearest Neighbor Search (EEENNS) Method and Improved Equal-Average Equal-Variance Nearest Neighbor Search (IEENNS) Method for Fast Encoding of Vector Quantization(Image Processing and
- Fast Encoding Method for Image Vector Quantization Based on Multiple Appropriate Features to Estimate Euclidean Distance
- A Fast Encoding Method for Vector Quantization Using Modified Memory-Efficient Sum Pyramid
- A Fast Search Method for Vector Quantization Using Enhanced Sum Pyramid Data Structure(Image)
- An Improved Fast Encoding Algorithm for Vector Quantization Using 2-Pixel-Merging Sum Pyramid and Manhattan-Distance-First Check(Image Processing, Image Pattern Recognition)
- A Fast Encoding Method for Vector Quantization Using L_1 and L_2 Norms to Narrow Necessary Search Scope(Image Processing, Image Pattern Recognition)
- A Fast Encoding Method for Vector Quantization Based on 2-Pixel-Merging Sum Pyramid Data Structure(Image)
- A nonlinear cepstral compensation method for noisy speech processing (音声言語情報処理 研究報告 第1回音声言語シンポジウム(SPLC))
- Extracting person's speech individually from original records of meeting by speaker identification technique
- Control of nitrogen profile in radical nitridation of SiO_2 films
- Tribological study for low shear force CMP process on damascene interconnects (シリコン材料・デバイス)
- Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology (Special Issue on Integrated Electronics and New System Paradigms)
- A Comparative Examination of Ion Implanted n^+p Junctions Annealed at 1000℃ and 450℃
- Effect of Substrate Boron Concentration on the Integrity of 450℃-Annealed Ion-Implanted Junctions
- Reducing Reverse-Bias Current in 450℃-Annealed n^+p Junction by Hydrogern Radical Sintering
- Impact of fully depleted silicon-on-insulator accumulation-mode CMOS on Si(110) (シリコン材料・デバイス)
- Neuron MOS Analog/Digital Merged Circuit Technology For Center-Of-Mass Tracker Circuit
- Oscillatory High-Field Magnetization in LaP Doped with Ce
- Performance Comparison of Ultra-thin FD-SOI Inversion-, Intrinsic- and Accumulation-Mode MOSFETs
- An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations
- Highly Reliable MOS Trench Gate FET by Oxygen Radical Oxidation
- Improved J-E Characteristics and Stress Induced Leakage Currents (SILC) in Oxynitride Films Grown at 400℃ by Microwave-Excited High-Density Kr/O_2/NH_3 Plasma
- Low Temperature Gate Oxidation MOS Transistor Produced by Kr/O_2 Microwave Excited High-Density Plasma
- Ultra-Thin Silicon Oxynitride Film Grown at Low-Temperature by Microwave-Excited High-Density Kr/O_2/N_2 Plasma
- Ultra-Thin Silicon Oxynitride Films as Cu Diffusion Barrier for Lowering Interconnect Resistivity
- High-Integrity Silicon Oxide Grown at Low-Temperature by Atomic Oxygen Generated in High-Density Krypton Plasma
- Low-Temperature Formation of Silicon Nitride Film by Direct Nitridation Employing High-Density and Low-Energy Ion Bombardment
- Effect of in-situ Formed Interlayer at Ta-SiO_2 interface on Performance and Reliability in Ta-Gate MOS Devices
- A Fine-Grained Programmable Logic Module with Small Amount of Configuration Data for Dynamically Reconfigurable Field-Programmable Gate Array
- Study on Compositional Transition Layers at Gate Dielectrics/Si Interface by using Angle-resolved X-ray Photoelectron Spectroscopy
- Study on Compositional Transition Layers at Gate Dielectrics/Si Interface by using Angle-resolved X-ray Photoelectron Spectroscopy
- Thin and Low-Resistivity Tantalum Nitride Diffusion Barrier and Giant-Grain Copper Interconnects for Advanced ULSI Metallization
- Thin and Low-Resistivity Tantalum Nitride Diffusion Barrier and Giant-Grain Copper Interconnects for Advanced ULSI Metallization
- Nitrogen Profile Study for SiON Gate Dielectrics of Advanced DRAM
- A Compact Memory-Merged Vector-Matching Circuitry for Neuron-MOS Associative Processor (Special Issue on Integrated Electronics and New System Paradigms)
- Data Analysis Technique of Atomic Force Microscopy for Atomically Flat Silicon Surfaces
- Low Contact Resistance with Low Schottky Barrier for N-type Silicon Using Yttrium Silicide
- Very Low Bit Error Rate in Flash Memory using Tunnel Dielectrics formed by Kr/O_2/NO Plasma Oxynitridation
- PVD Tantalum Oxide with Buffer Silicon Nitride Stacked High-k MIS Structure Using Low Temperature and High Density Plasma Processing
- Improved Transconductance and Gate Insulator Integrity of MISFETs with Si_3N_4 Gate Dielectric Fabricated by Microwave-Excited High-Density Plasma at 400℃
- Low Resistivity PVD TaNx/Ta/TaNx Stacked Metal Gate CMOS Technology Using Self-Grown bcc-Phased Tantalum on TaNx Buffer Layer
- A Statistical Analysis of Distributions of RTS Characteristics by Wide-Range Sampling Frequencies
- A Statistical Analysis of Distributions of RTS Characteristics by Wide-Range Sampling Frequencies
- A Material of Semiconductor Package with Low Dielectric Constant, Low Dielectric Loss and Flat Surface for High Frequency and Low Power Propagation(Session2: Silicon Devices I)
- A Material of Semiconductor Package with Low Dielectric Constant, Low Dielectric Loss and Flat Surface for High Frequency and Low Power Propagation(Session2: Silicon Devices I)
- The Evaluation of New Amorphous Hydrocarbon Film aCHx, for Copper Barrier Dielectric Film in Low-k Copper Metallization
- Low Dielectric Constant Non-Porous Fluorocarbon Films for Inter-Layer Dielectric
- A Large-Signal MOSFET Model Based on Transient Carrier Response for RF Circuits
- A High S/N Ratio Object Extraction CMOS Image Sensor with Column Parallel Signal Processing
- Analysis of High-Speed Signal Behavior in a Miniaturized Interconnect(Special Issue on Advanced Sub-0.1μm CMOS Devices)
- Interconnect and Substrate Structure for High Speed Giga-Scale Integration
- Characterization of Zinc Oxide Films Grown by a Newly Developed Plasma Enhanced MOCVD Employing Microwave Excited High Density Plasma
- Damage-Free Microwave-Excited Plasma Contact Hole Etching without Carrier Deactivation at the Interface between Silicide and Heavily-Doped Si
- Influence of Interface Structure on Oxidation Rate of Silicon : Surfaces, Interfaces, and Films
- Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Study on Reclaimed Photoresist Developer Using an Electrodialysis Method
- A Study on Reclaimed Photoresist Developer Using an Electrodialysis Method
- Manufacturing Process of Flat Display(Micro Mechanical Engineering)
- Sonoluminescence measurement of 1MHz ultrasonic cavitation and effect of dissolved gases
- Ultrashallow and Low-Leakage p^+n Junction Formation by Plasma Immersion Ion Implantation (PIII) and Low-Temperature Post-Implantation Annealing
- Ultra-Shallow and Low-Leakage p^+n Junctions Formation by Plasma Immersion Ion Implantation (PIII) and Low-Temperature Post-Implantation Annealing
- A Dynamically Reconfigurable Processor with Multi-Mode Operation Based on Newly Developed Full-Adder/D-Flip-Flop Merged Module (FDMM)
- Minimizing Wafer Surface Damage and Chamber Material Contamination in New Plasma Processing Equipment
- Impurity Measurement in Specialty Gases Using an Atmospheric Pressure Ionizaiton Mass Spectrometer with a Two-Compartment Ion Source
- Impurity Measurement in Specialty Gases Using Atmospheric Pressure Ionization Mass Spectrometer with Two Compartments Ion Source
- An Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects
- Tribological effects of brush scrubbing in post chemical mechanical planarization cleaning on electrical characteristics in novel non-porous low-k dielectric fluorocarbon on Cu interconnects (Special issue: Advanced metallization for ULSI applications)
- Hot-Carrier-Immunity Degradation in Metal Oxide Semiconductor Field Effect Transistors Caused by Ion-Bombardment Processes
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (画像工学)
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (信号処理)
- New compact and power-efficient implementations of rank-order-filters and sorting engines using time-domain computation technique (集積回路)
- A Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible MIMD Elements
- A High-Performance Ramp-Voltage-Scan Winner-Take-All Circuit in an Open Loop Architecture
- A High-Performance Time-Domain Winner-Take-All Circuit Employing OR-Tree Architecture
- Automatic Defect Pattern Detection on LSI Wafers Using Image Processing Techniques
- Optimizing Vector-Quantization Processor Architecture for Intelligent Query-Search Applications
- Optimizing Associative Processor Architecture for Intelligent Internet Search Applications
- A Compact and Power-Efficient Implementation of Rank Order Filters Using Time-Domain Digital Computation Technique
- Neuron-MOS Parallel Search Hardware for Real-Time Signal Processing
- Superior Generalization Capability of Hardware-Learing Algorithm Developed for Self-Learning Neuron-MOS Neural Networks
- Intelligent Signal Processing Based on a Psychologically-Inspired VLSI Brain Model(Special Section on the Trend of Digital Signal Processing and Its Future Direction)
- Functionality Enhancement in Elemental Devices for Implementing Intelligence on Integrated Circuits (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Moving-Object-Localization Hardware Algorithm Employing OR-Amplification of Pixel Activities
- A Compact Bell-Shaped Analog Matching Cell Module for Digital-Memory-Based Associative Processors
- Four-Terminal Device Electronics for Intelligent Silicon Integrated Systems
- An Edge Cache Memory Architecture for Early Visual Processing VLSIs
- FOREWORD (Special Section on Digital Signal Processing)
- Hardware Architecture for Pseudo-2D Hidden-Markov-Model-Based Face Recognition System Employing Laplace Distribution Functions
- Compact Bell-Shaped Analog Matching-Cell Module for Digital-Memory-Based Associative Processors
- A Hardware-Implementation-Friendly Pulse-Coupled Neural Network Algorithm for Analog Image-Feature-Generation Circuits
- A Simple Random Noise Generator Employing Metal-Oxide-Semiconductor-Field-Effect-Transistor Channel $kT/C$ Noise and Low-Capacitance Loading Buffer
- Hardware Architecture for Pseudo-Two-Dimensional Hidden-Markov-Model-Based Face Recognition Systems Employing Laplace Distribution Functions
- Moving-Object-Localization Hardware Algorithm Employing OR-Amplification of Pixel Activities
- Real-Time Very Large-Scale Integration Recognition System with an On-Chip Adaptive K-Means Learning Algorithm
- Compact and Power-Efficient Implementation of Rank-Order Filters Using Time-Domain Digital Computation Technique