Efficient Image-Vector-Generation Processor for Edge-Based Complementary Feature Representations
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概要
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A digital processor dedicated to edge-based image vector generation has been developed aiming at real-time image recognition. The processor consists of an on-chip memory and 16 single instruction multiple data (SIMD) processing elements. The capacity of the on-chip memory as well as the overhead for starting the processing have been minimized by introducing a seamless data transferring scheme from memory to processing elements. The 16 SIMD processing elements work together either as accumulators or as shift registers, thus achieving a very efficient generation of two different kinds of feature vector: projected principal-edge distribution (PPED) 3,4 and averaged principal-edge distribution (APED). 5 Concurrent use of these two vectors is shown to be very important for robust image recognition. 5 The chip was fabricated using 0.18-μm complementary metal oxide semiconductor (CMOS) technology and the generation of 64-dimension PPED and APED vectors at 84.7 and 83.9 fps, respectively, from video graphics array (VGA) size images was demonstrated at 62.5 MHz.
- 2012-02-25
著者
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Yamashita Naoya
Department of Electrical Engineering and Information Systems, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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Shibata Tadashi
Department of Electrical Engineering and Information System, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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