A Hardware-Implementation-Friendly Pulse-Coupled Neural Network Algorithm for Analog Image-Feature-Generation Circuits
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概要
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Pulse-coupled neural networks (PCNNs) are biologically inspired algorithms that have been shown to be highly effective for image feature generation. However, conventional PCNNs are software-oriented algorithms that are too complicated to implement as very-large-scale integration (VLSI) hardware. To employ PCNNs in image-feature-generation VLSIs, a hardware-implementation-friendly PCNN is proposed here. By introducing the concepts of exponentially decaying output and a one-branch dendritic tree, the new PCNN eliminates the large number of convolution operators and floating-point multipliers in conventional PCNNs without compromising its performance at image feature generation. As an analog VLSI implementation of the new PCNN, an image-feature-generation circuit is proposed. By employing floating-gate metal–oxide–semiconductor (MOS) technology, the circuit achieves a full voltage-mode implementation of the PCNN in a compact structure. Inheriting the merits of the PCNN, the circuit is capable of generating rotation-independent and translation-independent features for input patterns, which has been verified by SPICE simulation.
- 2007-04-30
著者
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Shibata Tadashi
Department Of Electrical Engineering And Information Systems School Of Engineering The University Of
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Chen Jun
Department Of Biomedical Engineering Division Of Orthopaedic Surgery Department Of Surgery Duke University
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Shibata Tadashi
Department of Frontier Informatics, School of Frontier Science, The University of Tokyo, 5-15 Kashiwanoha, Kashiwa, Chiba 277-8561, Japan
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Chen Jun
Department of Electronic Engineering, Graduate School of Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan
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Shibata Tadashi
Department of Electrical Engineering and Information System, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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