Metal Schottky Source/Drain Technology for Ultrathin Silicon-on-Thin-Box Metal Oxide Semiconductor Field Effect Transistors

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This paper reports novel, non-epitaxial raised source/drain (S/D) approaches to decrease the parasitic external resistance in complementary metal--oxide--semiconductor field-effect transistors (CMOSFETs) fabricated on ultrathin silicon on insulator (UTSOI). This technique utilizes a metal Schottky S/D process with dopant segregation. Selectively formed NiSi2 with dopant segregation fabricated by laser-spike annealing (LSA) significantly lowered effective Shottky-barrier height and, thereby, lowered contact resistance ($\rho_{\text{c}}$). Satisfying the requirements of UTSOI MOSFETs in the 32-nm node for low stand-by power (LSTP) application, external parasitic resistance was reduced to 140 (NMOS) and 350 (PMOS) $\Omega$ μm. Our results show that $\rho_{\text{c}}$ is an important component of parasitic resistance in terms of improving device performance of UTSOI MOSFETs.
2011-04-25