The Umbrella Cell : A High-Density 2T Cell for SOC Applications(Memory, <Special Section>Low-Power LSI and Low-Power IP)

スポンサーリンク

概要

• 論文の詳細を見る

• To realize a high-density on-chip memory, the authors have proposed a novel logic-process-compatible memory cell. This cell consists of two logic transistors, and placing a planar MIM (metal insulator metal) capacitor on a copper wire above the transistors produces a memory area of 26 F^2, which is approximately 60% smaller than a 6T SRAM cell. A suitable cell-bias design and a dual precharge scheme solve the coupling problem inherent in the cell and allow standard logic transistors to be used. This cell-applying the proposed schemes-can handle 10-ns cycle time at a bit-line voltage of 0.7 V. The random cycle is about three times faster than that of a conventional V_<BL> precharge scheme. These results indicate that the umbrella cell is a strong candidate for providing a high-density memory for SOC applications.

• 社団法人電子情報通信学会の論文
• 2005-04-01

著者

• WATANABE Takao

  Central Research Laboratory, Hitachi Ltd.

• HISAMOTO Digh

  Central Research Laboratory, Hitachi, Ltd.

• OODAIRA Nobuhiro

  Hitachi ULSI Systems Co., Ltd.

• Hisamoto Digh

  Central Research Laboratory Hitachi Ltd.

• AKIYAMA Satoru

  Central Research Laboratory, Hitachi, Ltd.

• Akiyama Satoru

  Central Research Laboratory Hitachi Ltd.

• ISHIKAWA Tsuyoshi

  Waseda University

• Akiyama Satoru

  Hitachi Ltd. Kokubunji‐shi Jpn

• Oodaira Nobuhiro

  Hitachi Ulsi Systems Co. Ltd.

• Watanabe Takao

  Central Research Lab. Hitachi Ltd.

• Watanabe Takao

  Central Research Laboratory Hitachi Ltd.

関連論文

• Low-Power and High-Speed Advantages of DRAM-Logic Integration for Multimedia Systems (Special Issue on Low-Power and High-Speed LSI Technologies)
• Electro-Luminescence from Ultra-Thin Silicon
• μI/O Architecture : A Power-Aware Interconnect Circuit Design for SoC and SiP(Low-Power System LSI, IP and Related Technologies)
• Amorphous Channel SESO Memory with Good Logic Process Compatibility for Low-power High-density Embedded RAM
• Long-Retention-Time, High-Speed DRAM Array with 12-F^2 Twin Cell for Sub 1-V Operation(Memory,Low-Power, High-Speed LSIs and Related Technologies)
• The Umbrella Cell : A High-Density 2T Cell for SOC Applications(Memory, Low-Power LSI and Low-Power IP)
• The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips
• 3-D CG Media Chip : An Experimental Single-Chip Architecture for Three-Dimensional Computer Graphics (Special Issue on Multimedia, Analog and Processing LSIs)
• Metal Schottky Source/Drain Technology for Ultrathin Silicon-on-Thin-Box Metal Oxide Semiconductor Field Effect Transistors
• Surface-Reaction-Controlled Tungsten CVD Technology for 0.1-µm Low-Resistive, Encroachment-Free CMOS-FET Applications
• Surface Reaction Controlled W-CVD Technology for 0.1-μm Low-Resistive, Encroachment-Free CMOS-FET Applications
• Electro-Luminescence from Ultra-Thin Silicon
• A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
• A Low-V_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing

もっと見る 閉じる

スポンサーリンク