μI/O Architecture : A Power-Aware Interconnect Circuit Design for SoC and SiP(<Special Section>Low-Power System LSI, IP and Related Technologies)

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概要

• 論文の詳細を見る

• A power-aware interconnect circuit design-called μI/O architecture-has been developed to provide low-cost system solutions for System-on-Chip (SoC) and System-in-Package (SiP) technologies. The μI/O architecture provides a common interface throughout the module enabling hierarchical I/O design for SoC and SiP. The hierarchical I/O design allows the driver size to be optimized without increasing design complexity. Moreover, it includes a signal-level converter for integrating wide-voltage-range circuit blocks and a signal wall function for turning off each block independently-without invalid signal transmission-by using an internal power switch.

• 社団法人電子情報通信学会の論文
• 2004-04-01

著者

• Kanno Yusuke

  System Lsi Research Department Central Research Laboratory Hitachi Ltd.

• Mizuno H

  System Lsi Research Department Central Research Laboratory Hitachi Ltd.

• MIZUNO Hiroyuki

  System LSI Research Department, Central Research Laboratory, Hitachi, Ltd.

• OODAIRA Nobuhiro

  Hitachi ULSI Systems Co., Ltd.

• YASU Yoshihiko

  Renesas Technology Co.

• YANAGISAWA Kazumasa

  Renesas Technology Co.

• Mizuno Hiroyuki

  System Lsi Research Department Central Research Laboratory Hitachi Ltd.

• Oodaira Nobuhiro

  Hitachi Ulsi Systems Co. Ltd.

関連論文

• μI/O Architecture : A Power-Aware Interconnect Circuit Design for SoC and SiP(Low-Power System LSI, IP and Related Technologies)
• Investigations of Optimum Tier Architectures for ASICs(VLSI Design Technology and CAD)
• The Umbrella Cell : A High-Density 2T Cell for SOC Applications(Memory, Low-Power LSI and Low-Power IP)

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