Long-Retention-Time, High-Speed DRAM Array with 12-F^2 Twin Cell for Sub 1-V Operation(Memory,<Special Section>Low-Power, High-Speed LSIs and Related Technologies)

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概要

• 論文の詳細を見る

• A DRAM-cell array with 12-F^2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1V and keeps the retention time of the single-cell array at 0.4V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4V.

• 社団法人電子情報通信学会の論文
• 2007-04-01

著者

• SEKIGUCHI Tomonori

  Central Research Laboratory, Hitachi, Ltd.

• Kawahara Takayuki

  Central Research Laboratory Hitachi Ltd.

• TAKEMURA Riichiro

  Central Research Laboratory, Hitachi, Ltd.

• ITOH Kiyoo

  Central Research Laboratory, Hitachi, Ltd.

• AKIYAMA Satoru

  Central Research Laboratory, Hitachi, Ltd.

• HANZAWA Satoru

  Central Research Laboratory, Hitachi, Ltd.

• KAJIGAYA Kazuhiko

  ELPIDA Memory, Inc.

• Itoh Kiyoo

  Hitachi Ltd. Kokubunji‐shi Jpn

• Itoh Kiyoo

  Central Research Lab. Hitachi Ltd.

• Akiyama Satoru

  Central Research Laboratory Hitachi Ltd.

• Hanzawa Satoru

  Central Research Laboratory Hitachi Ltd.

• Takemura Riichiro

  Central Research Laboratory Hitachi Ltd.

• Kajigaya Kazuhiko

  Elpida Memory Inc.

• Sekiguchi Tomonori

  Central Research Laboratory Hitachi Ltd.

• Sekiguchi Tomonori

  Hitachi Europe Ltd.

関連論文

• Adaptive Circuits for the 0.5-V Nanoscale CMOS Era
• A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
• A High-Endurance Read/Write Scheme for Half-V_cc Plate Nonvolatile DRAMs with Ferroelectric Capacitors(Special Issue on Nonvolatile Memories)
• High-Reliability Programming Method Suitable for Flash Memories of More Than 256Mb
• Low-Voltage Embedded RAMs in Nanometer Era(Memory,Low-Power, High-Speed LSIs and Related Technologies)
• Electric-Energy Generation through Variable- Capacitive Resonator for Power-Free LSI(Low-Power System LSI, IP and Related Technologies)
• Long-Retention-Time, High-Speed DRAM Array with 12-F^2 Twin Cell for Sub 1-V Operation(Memory,Low-Power, High-Speed LSIs and Related Technologies)
• Dynamic Terminations for Low-Power High-Speed Chip Interconnection in Portable Equipment
• The Umbrella Cell : A High-Density 2T Cell for SOC Applications(Memory, Low-Power LSI and Low-Power IP)
• FOREWORD (Special Issue on ULSI Memory Technology)
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• A Robust Array Architecture for a Capacitorless MISS Tunnel-Diode Memory(Integrated Electronics)
• The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips
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• A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
• 0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs
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